similar to: [LLVMdev] mips16 patch8

On 02/04/2014 09:49 AM, Rafael Espíndola wrote: > On 4 February 2014 12:37, reed kotler <rkotler at mips.com> wrote: >> How is alignment set? > Of a symbol? EmitValueToAlignment. > > A tip on how to find this is to look at what clang prints > (".align...") and grep for it "git grep '\.align'"). > > Cheers, > Rafael Not on a symbol but

I'm rewriting this patch for the stubs to not use outputing of raw text. Generating the instructions is very straightforward and that part is done. I'm translating the actual function now. How do you emit an .ent or .globl from asm printer? .type ? .end ?? .section ??? I'm studying the classes now but it should be simple to do so if you know, you can save me some time because this

How is alignment set? On 02/04/2014 08:48 AM, Rafael Espíndola wrote: > On 31 January 2014 18:59, reed kotler <rkotler at mips.com> wrote: >> I'm rewriting this patch for the stubs to not use outputing of raw text. >> >> Generating the instructions is very straightforward and that part is done. > awesome! > >> I'm translating the actual function

On 01/08/2013 01:48 PM, Eli Friedman wrote: > On Mon, Jan 7, 2013 at 6:07 PM, reed kotler <rkotler at mips.com> wrote: >> For example: >> >> /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel >> -relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float > Try something like the following: > > float f; > double test(void*

On Tue, Jan 8, 2013 at 6:33 PM, reed kotler <rkotler at mips.com> wrote: > On 01/08/2013 01:48 PM, Eli Friedman wrote: >> >> On Mon, Jan 7, 2013 at 6:07 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> For example: >>> >>> /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel >>> -relocation-model=pic -o

For example: /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel -relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float On 01/04/2013 07:45 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler

On Mon, Jan 7, 2013 at 6:07 PM, reed kotler <rkotler at mips.com> wrote: > > For example: > > /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel > -relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float Try something like the following: float f; double test(void* fptr) { f = ((float(*)(float,float))fptr)(1.0, 1.0); } -Eli

So I have dual mode 16/32 compilation on a per function basis working. I need to clean up some things and then will push the change. I managed to do everything without needing to change anything in target independent code thus far. It was a fun puzzle to solve as to how to do this using only the given APIs. As for the BasicTransformInfoPassass, for this dual mode I'm using

On Sep 20, 2012, at 11:44 PM, Reed Kotler <rkotler at mips.com> wrote: > Actually, SP is already not in the mips 16 register class but there is some C++ code that is common to mips32, mips64 and mips16 that is wanting to use SP. It's kind of awkward but does work except in this case of load/store haflword and byte to stack objects. > ARM has a similar problem. The InstrInfo

On Mon, Jan 7, 2013 at 4:16 PM, reed kotler <rkotler at mips.com> wrote: > On 01/04/2013 07:45 PM, Eli Friedman wrote: >> >> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>>> >>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com>

On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: > On 01/04/2013 06:08 PM, Eli Friedman wrote: >> >> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> I'm working on mips16 hard float which at a first approximation is just >>> soft >>> float but calls different library

On 03/28/2013 12:22 PM, Nadav Rotem wrote: > Hi Reed, > > On Mar 28, 2013, at 12:18 PM, Reed Kotler <rkotler at mips.com > <mailto:rkotler at mips.com>> wrote: > >> As for the BasicTransformInfoPassass, for this dual mode I'm using >> createNoTargetTransformInfoPass right now. > > So, MIPS does not need LSR, LowerSwitch and other optimizations

Actually, SP is already not in the mips 16 register class but there is some C++ code that is common to mips32, mips64 and mips16 that is wanting to use SP. It's kind of awkward but does work except in this case of load/store haflword and byte to stack objects. Maybe I'm shooting myself in the foot there. I don't know that code too well so maybe I need to look into it. There are

On 02/04/2014 09:58 AM, Rafael Espíndola wrote: >> .align > > So yes, EmitValueToAlignment. > > Cheers, > Rafael > One more::: OutStreamer.EmitRawText("\t.size __call_stub_fp_" + Twine(Symbol) + ", .-__call_stub_fp_" + Twine(Symbol)); You have to make an expression???? i.e. .size __call_stub_fp___floatdidf,

On 01/04/2013 07:45 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >>>> I'm working on mips16 hard float which at a first approximation is just >>>> soft

Turned out to be a rather simple fix. Just copied SP to a virtual register in the beginning of the function. Then added an extra operand to the DAGs with stack reference load/store, with the extra operand equal to this virtual register if the Parent of the address is a LOAD/STORE of an 8 or 16 bit quantity. It worked fine. When needed SP got copied to a mips 16 register and when the SP alias

Reed, It's not clear to me that you need to do anything special here. If you define your MIPS16 register class as not containing SP, then any MIPS16 instructions that get selected and want to read from SP should get a COPY inserted from SP to a MIPS16 vreg. The coalescer should, ideally, get rid of extraneous copies for you. --Owen On Sep 20, 2012, at 10:48 PM, Reed Kotler <rkotler at

On 01/04/2013 06:08 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >> I'm working on mips16 hard float which at a first approximation is just soft >> float but calls different library routines. Those different library routines >> are just an implementation (in mips32 mode) of soft float using mips32 >>

Hi Reed, On Mar 28, 2013, at 12:18 PM, Reed Kotler <rkotler at mips.com> wrote: > As for the BasicTransformInfoPassass, for this dual mode I'm using createNoTargetTransformInfoPass right now. So, MIPS does not need LSR, LowerSwitch and other optimizations that depend on TTI ? > I will solve this issue of the BasicTransformInfoPass being immutable after this initial checking

Trying to think of a clever way to do something.... On Mips 16, the SP (stack pointer) is not a directly accessible register in most instructions. There is a way to move to and from mips 16 registers (subset of mips32) and mips32 registers. For the load/store word instructions, there are forms which implicitly take SP. However, for store/load byte and store/load halfword, there is no such