similar to: [LLVMdev] Match operands

On May 22, 2012, at 8:05 AM, "Medic, Vladimir" <vmedic at mips.com> wrote: > I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. > In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register. > For example ceil.w.s

Hi all, Just tried to build from svn sources with Visual Studio 2008, mostly OK but fails building the X86AsmParser lib - I see a few commits from yesterday that may have something to do with it, but no idea what the solution is. -David See MSVC's beautiful and concise output below; Compiling... X86AsmParser.cpp C:\dev\MSVisualStudio\VC\include\xutility(313) : error C2664: 'bool

On Sep 6, 2010, at 10:50 PM, David Shipman wrote: > Hi all, > > Just tried to build from svn sources with Visual Studio 2008, mostly > OK but fails > building the X86AsmParser lib - > > I see a few commits from yesterday that may have something to do with it, but no > idea what the solution is. Wow, that's a pretty terrible diagnostic. Does r113198 help? -Chris

Hello, I've been building Clang under Windows 7 and Visual Studio 2008 for a while now, but had not touched it in a few months. Last night I wiped my build tree to do a full rebuild with the latest version, and got the identical error as David Shipman was seeing last September. Are others able to build under VS9 right now? Thanks, John > Subject: Re: [LLVMdev] MS VS2008 build fails -

Hello, About a month ago, I submitted a set of patches for review on llvm-commit. The most controversial of the patches, http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20150622/d104ea7 1/attachment-0009.obj deals with the fact that before ARMv8, the rGPR RegClass in Thumb encodings didn't include SP; but from ARMv8 onwards, it does include it. RegClass membership is

Hi, after perusing through llc -debug output and stepping through the ARMGenDAGIsel.inc in the debugger, I would greatly like some help in tracking down a failing match to a pattern I specified: First, here is a snippet of a successful match (done in ARM mode) ISEL: Starting pattern match on root node: 0x1e7adf0: i32,ch = load 0x1e4c030, 0x1e78210, 0x1e78310<LD4[ConstantPool]> [ID=10]

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>

Hi, I'd like to modify MachineBasicBlock contents within a MachineFunctionPass on the basis of how many CPU cycles the assembly instructions corresponding to the MBB take. I'm using the AVR backend and the number of CPU cycles every AVR assembly operation takes is openly available. Is there any straightforward way of getting the opcode mnemonics corresponding to a MachineInstr? I've

Hi, Mips32 has 64 bit floating point instructions, while i64 instructions have to be emulated with i32 instructions. This means that G_LOAD should be custom legalized for s64 integer value, and be legal for s64 floating point value. There are also other generic instructions with the same problem: G_STORE, G_SELECT, G_EXTRACT, and G_INSERT. There are also other configurations where integer