Displaying 20 results from an estimated 4000 matches similar to: "[LLVMdev] Bug in SUB expansion going back to LLVM 2.6"
2012 May 21
0
[LLVMdev] Bug in SUB expansion going back to LLVM 2.6
On May 21, 2012, at 11:21 AM, Villmow, Micah wrote:
> I found a bug in the expansion code for SUB going back to at least LLVM 2.6 and still shows up in trunk.
> case ISD::SUB: {
> EVT VT = Node->getValueType(0);
> assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
> TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
> "Don't
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 Dec 22
2
[LLVMdev] LegalizeDAG Error?
The LegalizeDAG.cpp file has this code in SelectionDAGLegalize::PromoteNode:
case ISD::BSWAP: {
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2009 Dec 22
0
[LLVMdev] LegalizeDAG Error?
On Dec 22, 2009, at 2:38 PMPST, Bill Wendling wrote:
> The LegalizeDAG.cpp file has this code in
> SelectionDAGLegalize::PromoteNode:
>
> case ISD::BSWAP: {
> unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
> Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
> Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
> Tmp1 = DAG.getNode(ISD::SRL, dl,
2009 Dec 01
0
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
Hi Javier,
> The problem is the implementation of the expansion. Perhaps an example
> can help illustrate better. Take the case of a 64-bit integer shifted
> left by say 6 bits and is decomposed using 32-bit registers. Because 6
> is less than the 32 (the register size) the resulting low part should be
> equal to the source low part shifted left by 6 bits. The current
>
2017 Apr 21
2
[cfe-dev] FE_INEXACT being set for an exact conversion from float to unsigned long long
I think it’s generally true that whenever branches can reliably be predicted branching is faster than a cmov that involves speculative execution, and I would guess that your assessment regarding looping on input values is probably correct.
I believe the code that actually creates most of the transformation you’re interested in here is in SelectionDAGLegalize::ExpandNode() in LegalizeDAG.cpp. The
2017 May 11
2
FENV_ACCESS and floating point LibFunc calls
Sounds like the select lowering issue is definitely separate from the FENV
work.
Is there a bug report with a C or IR example? You want to generate compare
and branch instead of a cmov for something like this?
int foo(float x) {
if (x < 42.0f)
return x;
return 12;
}
define i32 @foo(float %x) {
%cmp = fcmp olt float %x, 4.200000e+01
%conv = fptosi float %x to i32
%ret = select
2009 Dec 01
2
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
Hi Duncan,
The problem is the implementation of the expansion. Perhaps an example
can help illustrate better. Take the case of a 64-bit integer shifted
left by say 6 bits and is decomposed using 32-bit registers. Because 6
is less than the 32 (the register size) the resulting low part should be
equal to the source low part shifted left by 6 bits. The current
implementation places a zero
2017 May 11
3
FENV_ACCESS and floating point LibFunc calls
Thanks, Andy. I'm not sure how to solve that or my case given the DAG's
basic-block limit. Probably CodeGenPrepare or SelectionDAGBuilder...or we
wait until after isel and try to split it up in a machine instruction pass.
I filed my example here:
https://bugs.llvm.org/show_bug.cgi?id=33013
Feel free to comment there and/or open a new bug for the FP_TO_UINT case.
On Thu, May 11, 2017 at
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
>> Can you explain why you chose the approach of using a new pass?
>> I pictured removing LegalizeDAG's type legalization code would
>> mostly consist of finding all the places that use TLI.getTypeAction
2009 Dec 01
4
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
Hello,
I'm working in adding support for 64-bit integers to my target. I'm using
LLVM to decompose the 64-bit integer operations by using 32-bit registers
wherever possible and emulating support where not. When looking at the bit
shift decomposition I saw what seems to be a bug in the implementation. The
affected function is ExpandShiftWithUnknownAmountBit in
LegalizeIntegerTypes.cpp.
2013 Oct 03
2
[LLVMdev] Question about DAGCombiner::MatchRotate function
Hi all,
While I test
"clang-tests/gcc-4_2-testsuite/src/gcc.c-torture/execute/20020226-1.c",
I faced something wrong with "DAGCombiner::MatchRotate" function.
This function tries to consume some patterns and generate "ROTL" or
"ROTR" dag node as following comments:
"DAGCombier::MatchRotate" function in DAGCombiner.cpp
Pattern1
// fold (or
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
Per subject, this patch adding an additional pass to handle vector
operations; the idea is that this allows removing the code from
LegalizeDAG that handles illegal types, which should be a significant
simplification. There are still some issues with this patch, but does
the approach look sane?
-Eli
-------------- next part --------------
Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
2008 Sep 08
0
[LLVMdev] adde/addc
Richard Pennington wrote:
> My target doesn't support 64 bit arithmetic, so I'd like to supply
> definitions for adde/addc. The problem is I can't seem to figure out the
> magic. Here's an example of what I need to generate:
>
> # two i64s in r5/r6 and r7/r8
> # result in r1/r2, carry in r3
>
> # adde
> add r2, r6, r8
> cmpltu r3, r2, r6 #
2008 Sep 08
6
[LLVMdev] adde/addc
My target doesn't support 64 bit arithmetic, so I'd like to supply
definitions for adde/addc. The problem is I can't seem to figure out the
magic. Here's an example of what I need to generate:
# two i64s in r5/r6 and r7/r8
# result in r1/r2, carry in r3
# adde
add r2, r6, r8
cmpltu r3, r2, r6 # compute carry
# addc
add r1, r5, r7
add r1, zero, r3
Is this
2009 Dec 01
0
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote:
> Hello,
>
> I'm working in adding support for 64-bit integers to my target. I'm using
> LLVM to decompose the 64-bit integer operations by using 32-bit registers
> wherever possible and emulating support where not. When looking at the bit
> shift decomposition I saw what seems to be a
2012 Feb 10
1
[LLVMdev] Prevent DAG combiner from changing "store ConstFP, addr" to integer store
This code lives in DAGCombiner.cpp:
-------------
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
// NOTE: If the original store is volatile, this transform must not
increase
// the number of stores. For example, on x86-32 an f64 can be stored
in one
// processor operation but
2015 Aug 19
3
[RFC] Improving integer divide optimization (related to D12082)
Hello LLVM, A recent commit creates the isIntDivCheap() target query.
http://reviews.llvm.org/D12082
The current approach has a couple shortcomings.
First, when targets decide divide is cheap, the DAGCombiner ignores
obvious power-of-2 optimizations. In the targets I know, shifts are
cheaper than divides in both speed and size. The target cannot see
the value in the isIntDivCheap() call, so
2009 Jul 01
3
[LLVMdev] Inserting nodes into SelectionDAG (X86)
On Jul 1, 2009, at 2:22 PMPDT, Dan Gohman wrote:
>> Ops.push_back(DAG.getConstant(1, MVT::i32));
>> Chain = DAG.getNode(ISD::ADD, DAG.getVTList(MVT::Other, MVT::i32),
>> &Ops[0], Ops.size());
>>
>> Isn't that the way how it is supposed to work?
>
> ADD does not use a chain, so there's no chain operand, or
> MVT::Other result for it in an ADD