similar to: [LLVMdev] Inserting a branch in PPCTargetLowering::LowerFormalArguments_SVR4

I hate to be bothersome, but can someone please comment on this? Thanks again, Hal On Thu, 3 May 2012 14:49:04 -0500 Hal Finkel <hfinkel at anl.gov> wrote: > Hello, > > The current code in PPCTargetLowering::LowerFormalArguments_SVR4 > contains a FIXME over the code which saves the live floating-point > registers to the stack. The FIXME states that this should only be done

Hi Hal, For lowering code that requires inserting branches, you need to use a custom inserter, yes. Theoretically, that does indeed sound like what you want to do here. It's complicated by the general structure of argument passing, though. In particular, there's lots of assumptions about the call sequence stuff. I don't know if things are smart enough (EH in particular worries me) to

Jim, Thanks! Might it be possible to do this another way? For example, could I insert some special pseudo-instructions and then turn them into branches later on? -Hal On Thu, 10 May 2012 11:39:10 -0700 Jim Grosbach <grosbach at apple.com> wrote: > Hi Hal, > > For lowering code that requires inserting branches, you need to use a > custom inserter, yes. Theoretically, that

Hi Hal, Yes, you could definitely expand them later. Custom inserters are effectively just a very early expand pseudo instruction. You can even expand them very late in the MC lowering (asmprinter) if you really need to. That could get tricky, as you'll effectively be fibbing to the register allocator. ARM uses quite a lot of late expanded pseudo-instructions, for example, though generally

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

Ah, didn't see that, that's what comes of trying to do something at 5pm :) I attached an updated patch which creates a virtual register instead of using R0. How does this look? Cheers, Gary Dan Gohman wrote: > PPCTargetLowering::EmitInstrWithCustomInserter has a reference > to the current MachineFunction for other purposes. Can you use > MachineFunction::getRegInfo instead?

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

+ Eli Friedman as he often has very insightful comments regarding back end changes. On Fri, Jan 4, 2019 at 9:03 AM Nemanja Ivanovic <nemanja.i.ibm at gmail.com> wrote: > The changes seem fine to me. I don't think this is excessively intrusive > and it accomplishes what is needed by targets whose call lowering can > introduce illegal types. > Adding Justin Bogner as the

Evan Cheng wrote: > You need to insert new basic blocks and update CFG to accomplish this. > There is a hackish way to do this right now. Add a pseudo instruction > to represent this operation and mark it usesCustomDAGSchedInserter. > This means the intrinsic is mapped to a single (pseudo) node. But it > is then expanded into instructions that can span multiple basic >

Looks good. + unsigned temp; + if (is64bit) + temp = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); + else + temp = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); How about? const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : &PPC:G8RCRegClass; unsigned TmpReg = RegInfo.createVirtualRegister(RC); Evan On Jul 9, 2008, at 9:16 AM, Gary

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

Hi Robert, > I tried adding to the XCoreCallingConv.td: > CCIfByVal<CCPassByVal<0,4>> // pushes pointer to the stack This looks sensible to me. After that it comes down to cooperation between XCoreISelLowering's LowerFormalArguments and LowerCall functions. LowerFormalArguments is at the beginning of a function and is responsible for taking arguments out of

Cool, that worked. New patch attached... Cheers, Gary Evan Cheng wrote: > Just cast both values to const TargetRegisterClass*. > > Evan > > On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > > Evan Cheng wrote: > > > How about? > > > > > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > > > &PPC:G8RCRegClass; >

Hi, folks I am trying to build LLVM 2.8 Release on a Linux/PowerPC machine. Actually, the PowerPC is a PS3. Here is my system information: ---------------------------------------------------------------------- $ uname -a Linux ps3 2.6.32-rc2-00995-g96ebbe6-dirty #2 SMP Fri Oct 2 15:12:28 CST 2009 ppc64 Cell Broadband Engine, altivec supported GNU/Linux $ gcc --version gcc (Gentoo 4.3.2-r3

Hi Tim, Thank you for the input. I think I follow you. I believe the LowerCall is doing what it needs to do - passing pointer either on the stack or in register as per ABI. The LowerFormalArguments() is where I am stuck. LowerFormalArguments () calls CCInfo.AnalyzeFormalArguments(Ins, CC_XCore), which calls the CC_XCore(). This is where I placed the CCIfByVal<CCPassByVal<0,4>> which

On Tue, Apr 22, 2008 at 12:30 AM, Evan Cheng <evan.cheng at apple.com> wrote: > More nitpicks: > ... > No need for else here. :-) Done > SPDiff = (int)CallerMinReservedArea - (int)ParamSize; > > Just change last statement to > int SPDiff = (int)... Done > > +bool > +PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, > +

On Apr 16, 2008, at 10:07 AM, Arnold Schwaighofer wrote: > Hello Dale, > > this is an updated version of the tail call optimization patch for > powerpc. could you have a look at it? > > i added code to support ppc64 (untested, will try to get access to > ppc64 on a friend's machine). > incorporated evan's formatting suggestions. ;) > > will run another round

Hi Gary, The patch looks great. But I do have one comment: +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + let Uses = [R0] in + def ATOMIC_LOAD_ADD_I32 : Pseudo< The "let Uses = [R0]" is not needed. The pseudo instruction will be expanded like this later: + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) +

Hi Nemanja, I'm attaching a patch that builds on D54583 and implements what we discussed on IRC earlier today. Particularly: * Make LowerCallTo() a virtual function, so it can be wrapped by a subclass. * Implement LowerCallTo() in PPCTargetLowering to wrap TargetLowering::LowerCallTo() and legalize the return node when targeting SPE. * Augment PPCTargetLowering::LowerCall_32SVR4() to