similar to: [LLVMdev] form field in target specific td Instruction classes

>> Can I tell tablegen to have two encodings and switch between them >> using a predicate? After some deliberations, I modified tablegen to generate several versions of the GenCodeEmitter file. My tablegen now accepts a new command line parameter called "emitter-instfld". This specifies the name of the field in Instruction that holds the encoded bytes. In my target's td

Hello, I'm trying to write assembler code writer, and of course, have new questions. I'd like the structure my implementation like this: if (/*binary instruction*/) { // print destination O << " = "; // print first operand O << opcode; // print second operand. } if (/* unary instruction */ ) { .... } if (/*control instruction*/) { ....

I think we can get rid of the TSFlagsFields and TSFlagsShifts hack in the InstrInfo TableGen class now. This seems to work just fine: class Instruction { bits<32> TSFlags; } class Domain<bits<2> val> { bits<2> Value = val; } def GenericDomain : Domain<0>; def SSEPackedInt : Domain<1>; def SSEPackedSingle : Domain<2>; def SSEPackedDouble :

Hello LLVM, I'd like to check TSFlags in my AsmBackend code. However AsmBackend objects don't have a reference to MCInstrInfo, which is the only way I've seen to reach TSFlags. A quickie grep shows that none of the existing targets check TSFlags in their AsmBackends. Is there any reason I shouldn't check TSFlags in AsmBackend? If not, what's the best way to go about it?

Thank You. My add instruction has TA as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; so i defined; bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used

Hello, I am trying to emit binary for my implemented vector instructions. Although yet i havent done any change or addition in MC framework, For vector load instruction there are no error coming. But for vector add instruction is something like this; > %R_0_REG2048b_1<def> = P_256B_VADD %R_0_REG2048b_1<kill>, %R_0_REG2048b_0<kill> I am getting the following error: Unknown

You are right. But when i defined my instruction as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; I get opcode conflicts? Then what to do? On Tue, Sep 5, 2017 at 3:51 AM,

On 04/02/2013 03:31 PM, Reed Kotler wrote: > On 04/02/2013 03:00 PM, reed kotler wrote: >> How do you add a target dependent transform pass? >> >> tia. >> >> eed > > I need to add a module pass. Do you need to just add them to the Transform subdirectory????

----- Original Message ----- > From: "Reed Kotler" <rkotler at mips.com> > Cc: LLVMdev at cs.uiuc.edu > Sent: Wednesday, April 3, 2013 6:30:56 PM > Subject: Re: [LLVMdev] adding a target dependent transform pass > > On 04/02/2013 03:31 PM, Reed Kotler wrote: > > On 04/02/2013 03:00 PM, reed kotler wrote: > >> How do you add a target dependent

On Mon, 7 Jun 2004, Vladimir Prus wrote: > > Hello, > I'm trying to write assembler code writer, and of course, have new questions. > I'd like the structure my implementation like this: > if (/*binary instruction*/) { > if (/* unary instruction */ ) { > if (/*control instruction*/) { Okay, that should be no problem. > The question is how to write those

Sorry to ask but what does it mean to put both? On Tue, Sep 5, 2017 at 4:01 AM, Craig Topper <craig.topper at gmail.com> wrote: > Leave TA. Put both. > > ~Craig > > On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> You are right. But when i defined my instruction as follows: >> def P_256B_VADD : I<0xE1,

We are considering running clang format on the whole Mips target. Is there any rule against this? Is there any good argument against doing this even if there is no rule against it? TIA. Reed

I was getting same error when i keep both EVEX/EVEX_4V and TA. So, i restored my original instructions and for that i have to include bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; in order to emit binary correctly. Is it right? On Tue, Sep 5, 2017 at 5:45 AM, Craig Topper <craig.topper at gmail.com> wrote: >

Thank You. I used EVEX_4V with all the instructions. I replaced TA and EVEX both with EVEX_4V. Now, I am getting following error: llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void llvm::X86Disassembler::RecognizableInstr::emitInstructionSpecifier(): Assertion `numPhysicalOperands >= 2 + additionalOperands && numPhysicalOperands <= 4 + additionalOperands &&

Thank You, I changed TA to EVEX or EVEX_4V. But now i am getting following error: Invalid prefix! UNREACHABLE executed at /lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp:647! On Tue, Sep 5, 2017 at 4:36 AM, Craig Topper <craig.topper at gmail.com> wrote: > Not all instructions can use EVEX_4V. Move instructions in particular > cannot because they don't have 2 sources. >

Comments below. On Apr 15, 2008, at 4:24 AM, Nicolas Geoffray wrote: > OK, here's a new patch that adds the infrastructure and the > implementation for X86, ARM and PPC of GetInstSize and > GetFunctionSize. Both functions are virtual functions defined in > TargetInstrInfo.h. > > For X86, I moved some commodity functions from X86CodeEmitter to > X86InstrInfo. >

It seems like this code should work with Tablegen, but it generates the error: "error:Invalid TSFlags bit in ADD" Here's the code: =================================== include "llvm/Target/Target.td" def MyInstrInfo : InstrInfo; def MyTarget : Target { // Information about the instructions... let InstructionSet = MyInstrInfo; } def r1 :

Hi all, I suppose this is a very simple question, but as I've lost already a bit of time with it, without being able to get what I wanted, I'm addressing the question to the group in the hope someone can help me. I pretend to plot the richness of herbaceous species (RichHN) as a function of time since remnant isolation (Isol) conditioned to the area of the remnant (fArea - this is a

Okay to push this change? On 07/23/2013 05:17 PM, reed kotler wrote: > Hi Daniel, > > In this case we are not using lnt under Qemu user mode for benchmarking; > just as a way to run test-suite to test whether the code is correct. > > Qemu user mode emulates target instructions, but when it gets a Unix > Kernel trap, it uses the host to emulate those. > > For example,

When I query for installed package on the system, I get following result: # yum list installed openssl Loaded plugins: fastestmirror, tsflags, verify, versionlock Loading mirror speeds from cached hostfile Installed Packages openssl.x86_64 1.0.1e-16.el6_5.4 @updates/$releasever When I try to install already installed package (just playing with yum), I get following result: # yum install