similar to: [LLVMdev] Bug with debug information generation?

Filed as http://llvm.org/bugs/show_bug.cgi?id=12678. On Apr 23, 2012, at 2:03 PM, llvmdev-request at cs.uiuc.edu wrote: > I'm seeing some strange behavior with generating debugging information from a simple program. (LLVM top of tree, minus a couple of days.) > > I suspect that there is a bug in LLVM, but thought I'd check in here to see if perhaps I'm doing something

> On Jan 19, 2015, at 10:26 AM, Adrian Prantl <aprantl at apple.com> wrote: > > >> On Jan 19, 2015, at 10:08 AM, David Blaikie <dblaikie at gmail.com <mailto:dblaikie at gmail.com>> wrote: >> >> Hey guys, >> >> Frederic is introducing the expression dumping support and in the interests of tersity is skipping the "DW_" in every

> On Jan 19, 2015, at 10:34 AM, David Blaikie <dblaikie at gmail.com> wrote: > > > > On Mon, Jan 19, 2015 at 10:29 AM, Adrian Prantl <aprantl at apple.com <mailto:aprantl at apple.com>> wrote: > >> On Jan 19, 2015, at 10:26 AM, Adrian Prantl <aprantl at apple.com <mailto:aprantl at apple.com>> wrote: >> >> >>> On Jan

Hi,   I want to list some additional information on this.   The variable collection I am looking at is, "variables 'declared' in scope".   1. When I traverse the MachineInstructions in the LexicalScopes ranges, and check for variables, I get variables used in this scope.      The variables listed include variables which may not have been declared in the scope. (for example

Today Intel launched ispc, the Intel SPMD Program Compiler, an open-source compiler built on top of LLVM. It is available in both source and binary form from http://ispc.github.com/, under a BSD license. The goal of ispc is to provide a high-performance implementation of a C-based SPMD language for CPUs. The SPMD model has of course been quite successful for high-performance programming of

Hear hear. DW_ adds no readability but AT_/TAG_/OP_/etc do. Dropping the FORM entirely is fine; I view that as a mechanical encoding thing, not relevant to the informational content. If you're debugging the encoding then it would matter, but for a random string-value attribute it really doesn't matter which of the 3 (4?) different forms was used as long as the actual string shows up

I'm seeing some undesirable behavior where, when generating debugging information, sometimes the point in the debugger will jump forwards and backwards during single stepping, even though the output from our frontend (this is the ispc compiler), is emitting LLVM instructions with a strictly forward-moving/increasing set of source locations. I'm wondering if we're doing something wrong

On Jul 31, 2011, at 10:49 PM, Matt Pharr wrote: > I'm seeing some undesirable behavior where, when generating debugging information, sometimes the point in the debugger will jump forwards and backwards during single stepping, even though the output from our frontend (this is the ispc compiler), is emitting LLVM instructions with a strictly forward-moving/increasing set of source locations.

An addition for the publications page on llvm.org (and of potential interest to other people using LLVM for high-performance SIMD computation.) The ispc project would never have been possible without LLVM; many thanks to all involved in the LLVM project for building such a great system. Thanks, -matt ispc: A SPMD Compiler for High-Performance CPU Programming Matt Pharr and William R. Mark

I found the problem. The llvm.dbg.declare call must have a !dbg tag, otherwise the location info is not generated. Changing the invocation in my original example to "call void @llvm.dbg.declare(metadata !{i32* %"bar:Int32"}, metadata !13), !dbg !16" causes MC to generate the local location as expected. -Joe On Thu, Dec 29, 2011 at 12:41 PM, Joe Groff <arcata at

I figured out my previous problem with DIBuilder. However, now I can't seem to get the compiler to emit location information for local variables. Here's how my IR looks: --- define i32 @"\01_main"() { init: %exception1 = alloca i8* %0 = alloca i32 %"bar:Int32" = alloca i32 %1 = alloca i32 %2 = alloca i32* br label %code code:

I agree that a single vector index is sufficient for many cases. Matt Pharr (from the ISPC compiler), showed me an interesting case where there is a single pointer into an array. In this case we need to have two indices, where the first index is zero. Once the basic patch is in, we can start looking at adding support for arrays and multiple indices. Nadav -----Original Message----- From: David

Duncan, Thanks for the quick review! Here is a short description (design) of where I am going with this patch: 1. Motivation: Vectors-of-pointers is the first step in supporting scatter/gather instructions (available in AVX2, for example). I believe that this feature was requested on the mailing list before. As mentioned by Hal Finkel earlier today, this feature is desired by autovectorizers as

Hi Nadav, ISPC is generating long vectors (on corresponding ISPC targets) this way since the every beginning of ISPC as far as I know. There's no such things in official LLVM documents as "illegal vectors", so people do expect that arbitrary long vectors are supported and generated reasonably well. Note, not super-optimal, but reasonably well. Keeping it this way allows considering

Hi Dmitry, ISPC does some instruction selection as part of vectorization (on ASTs!) by placing intrinsics for specific operations. The SEXT to i32 pattern was implemented because LLVM did not support vector-selects when this code was written. Can you submit a small SSE4 test case that demonstrates the problem? Select is the canonical form of this operations, and SEXT is usually more

Hey guys, Frederic is introducing the expression dumping support and in the interests of tersity is skipping the "DW_" in every "DW_OP" (heck, we could even skip the "OP" given the context - nothing else textual can appear there, right?) Any thoughts on skipping the "DW_" (maybe even the AT/TAG/FORM too) in the rest of dwarfdump? (skipping the AT/TAG (FORM

Nadav, You are right, ISPC may issue intrinsics as a result of AST selection. Though I believe that we should stick to LLVM IR whenever is possible. Intrinsics may appear to be boundaries for optimizations (on both data and control flow) and are generally not optimizable. LLVM may improve over time from performance stand point and we would benefit from it (or it may play against us, like in this

Hi Dmitry. This looks like an ISPC workload. ISPC works around a limitation in selection dag which does not know how to legalize mask types when both 128 and 256 bit registers are available. ISPC works around this problem by expanding the mask to i32s and using intrinsics. Can you please verify that this regression only happens on AVX ? Can you change ISPC to use intrinsics ? Thanks Nadav Sent

Nadav, You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. For the rest we use general LLVM instructions. And I actually would really like to stick this way. We rely on LLVM's ability to produce efficient code from general LLVM IR. Relying on

Hi Dmitry, Yes, this is a known problem with legalizing vector masks. The type <8 x i1> is legalized to 8 x i16, on SSE, but your operands are legalized to <4 x i32>. Type-legalization is performed per-node and we don’t have a good way to support instructions that mix the mask and operand type. Why does ISPC generate illegal vector types ? Does ISPC rely on the LLVM codegen to