similar to: [LLVMdev] Effect of NSW attribute on 'mul' during InstCombine pass ?

Hi all, I'm using LLVM 3.0, for which I've filed following bug http://llvm.org/bugs/show_bug.cgi?id=12130. I'm trying to solve this problem by myself digging into LLVM sources. It seems that problem that I'm experiencing is related to presence or absence of NSW attribute on a 'mul'. Considering following code: define void @t2(double* %x) { L.entry: %a = alloca [2 x

Hi all, I'm using LLVM 3.0, for which I've filed following bug http://llvm.org/bugs/show_bug.cgi?id=12130. I'm trying to solve this problem by myself digging into LLVM sources. It seems that problem that I'm experiencing is related to presence or absence of NSW attribute on a 'mul'. Considering following code: define void @t2(double* %x) { L.entry: %a = alloca [2 x

Hi Seb, I think it is an opt bug. If you run opt at -O1 then you get: define void @t2(double* nocapture %x) nounwind { L.entry: %a = alloca [2 x i64], align 8 %0 = getelementptr inbounds [2 x i64]* %a, i32 0, i32 0 store i64 3, i64* %0, align 8 %1 = getelementptr [2 x i64]* %a, i32 0, i32 1 store i64 5, i64* %1, align 8 %2 = bitcast [2 x i64]* %a to double* %3 = load double*

Hi Duncan, Indeed, I made same experiment as you and concluded that it might be a BUG. Shall I submit it to llvm bug tracking support ? Do you think there could be a work-around ? Thanks for your quick answer. Best Regards Seb 2012/2/28 Duncan Sands <baldrick at free.fr> > Hi Seb, I think it is an opt bug. If you run opt at -O1 then you get: > > define void @t2(double*

According to comment in tree-nested.c, these frames should be only introduced in case of debug or OpenMP lowering: /* A subroutine of convert_nonlocal_reference_op. Create a local variable in the nested function with DECL_VALUE_EXPR set to reference the true variable in the parent function. This is used both for debug info and in OpenMP lowering. */ However, in this code example we

On Tue, Jul 30, 2013 at 01:14:16PM -0600, Dan wrote: > I'll try to run through the scenario: > > > 64-bit register type target (all registers have 64 bits). > > all 32-bits are getting promoted to 64-bit integers > > Problem: > > MUL on i32 is getting promoted to MUL on i64 > > MUL on i64 is getting expanded to a library call in compiler-rt > >

Hi Duncan, A DragonEgg/GCC-related question: do you know where these strange FRAME tokens originate from (e.g. %struct.FRAME.matmul)? Compiling simple Fortran code with DragonEgg: > cat matmul.f90 subroutine matmul(nx, ny, nz) implicit none integer :: nx, ny, nz real, dimension(nx, ny) :: A real, dimension(ny, nz) :: B real, dimension(nx, nz) :: C integer :: i, j, k real,

Thanks for the information, allow maybe I can re-phrase the question or issue. Assume 64-bit register types, but integer is 32-bit. Already have table generation of the 64-bit operation descriptions. How about this modified approach? Before type-legalization, I'd really like to move all MUL I64 to a subroutine call of my own choice. This would be a form of customization, but I want this

Hello, Everyone. I have a question about llvm's "Combine redundant instructions(instcombine)" pass. I have tested instcombine pass by writing the following three test cases. But, CASE3 is not optimized as I expected. Is this behavior expected? The version of llvm is: clang version 5.0.1 (tags/RELEASE_501/final 325232) Option of clang command is: clang -O1 a.c -S -emit-llvm

Dear, SelectionDAG developers, could you please comment on this issue and clarify internals of MUL lowering? Does my case (processor with soft MUL) supported by current design or such architectures are out of scope? How lowering of large MUL is supposed to work? What kind of minimalistic support should be provided by target back-end? What can be used from current LegalizeDAG? - Thanks, Sergey

I'll try to run through the scenario: 64-bit register type target (all registers have 64 bits). all 32-bits are getting promoted to 64-bit integers Problem: MUL on i32 is getting promoted to MUL on i64 MUL on i64 is getting expanded to a library call in compiler-rt the problem is that MUL32 gets promoted and then converted into a subroutine call because it is now type i64, even though

Hi all, I'm looking at following code snippet: void t2(double *x) { long long a[2]; a[0] = 3; a[1] = 5; *x = * ((double *) a); *(x+1) = * ((double *) &a[a[0]-2]); } I use generate LLVM code using my own front-end that looks like: ; ModuleID = 'jb.c' target datalayout =

Hi Jim, Thanks for the advice. Since I'm using LLVM 2.9 style of debug information. Will this code benefit from those improvement or should I generate LLVM 3.0 style of debug information ? Best Regards Seb 2012/3/6 Jim Grosbach <grosbach at apple.com> > > On Mar 6, 2012, at 5:31 AM, Seb <babslachem at gmail.com> wrote: > > Hi all, > > Anyone have ideas/info on

When I compile attached IR with LLVM 3.6 llc -march=x86-64 -o f.S f.ll it generates an aligned ADDPS with unaligned address. See attached f.S, here an extract: addq $12, %r9 # $12 is not a multiple of 4, thus for xmm0 this is unaligned xorl %esi, %esi .align 16, 0x90 .LBB0_1: # %loop2

On Thu, Jan 26, 2012 at 3:19 PM, Hal Finkel <hfinkel at anl.gov> wrote: > On Thu, 2012-01-26 at 15:12 -0600, Sebastian Pop wrote: >> On Thu, Jan 26, 2012 at 2:49 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> > Thanks! Did you compile with any non-default flags other than -mllvm >> > -vectorize? >> >> I used -O3 and -vectorize, no other non-default

I'm building tool-chain for processor without integer MUL. So, I've defined __mulsi3 for integer multiplication (int32). Now I've got a problem with int64 multiplication which is implemented in libgcc2.c. Segfualt due to infinite recursion in i64 soft multiplication (libgcc2, __muldi3). LLVM-GCC (for my target) misoptimizes code if -O2 is passed. It promotes i32 multiplication to

The loop vectorized does not estimate the cost of vectorization by looking at the IR you list below. It does not vectorize and then run the CostAnalysis pass. It estimates the cost itself before it even performs the vectorization. The way it works is that it looks at all the scalar instructions and asks: What is the cost if I execute the scalar instruction as a vector instruction. Therefore, it

Hi LLVM, 1. Can mul and/or div support be added for big integer types like i256? 2. What are the limits? 3. If yes, how should it be done? I have experience only with X86 target and know that mul i128 works and div i128 is lowered to function call from compile-rt like library (what works only if you link with such library). Can that support be extended? - Paweł -------------- next part

Well, I am much happier now that I understand about dsymutil, and can actually step through my program in gdb. However, there are still some issues that are puzzling me. 1) First off, the debugger appears to stop at odd points. The IR for my main function looks correct to me: define i32 @"main(tart.core.Array[tart.core.String])->int"(%"tart.core.Array[tart.core.String]"*

Hi all, Anyone have ideas/info on this topic ? Thanks Seb 2012/3/2 Seb <babslachem at gmail.com> > Hi all, > > I'm using my own front-end to generate following code .ll file targeting > x86 32-bit: > > ; ModuleID = 'check.c' > target datalayout = >