similar to: [LLVMdev] Hexagon llvm patch for V5- floating point support.

Here's a Hexagon cfe patch for floating point support. Please take some time to review this patch. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonV5-FP-Support-cfe.patch

Sure I can do that. In that case, let me recreate all the patches (along with the test cases) and put up the patches for review. sirish On 4/20/2012 4:16 PM, Eric Christopher wrote: > On Apr 20, 2012, at 1:58 PM, Sirish Pande<spande at codeaurora.org> wrote: > >> Here's a patch that contains Hexagon Test cases. Please review. > You can't include these in the

Here's a patch that contains Hexagon Test cases. Please review. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonTestCases.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120420/eb32dede/attachment.ksh>

On Apr 20, 2012, at 1:58 PM, Sirish Pande <spande at codeaurora.org> wrote: > Here's a patch that contains Hexagon Test cases. Please review. You can't include these in the patches that they're supposed to go along with? -eric

No test cases for a 500k patch? -eric On Apr 18, 2012, at 9:18 PM, Sirish Pande wrote: > Hi, > > Here's a patch for Hexagon Packetizer for review. This patch does not yield any warnings. > > Sirish > > -- > Qualcomm Innovation Center, Inc is a member of Code Aurora Forum > > <HexagonPacketizer.patch>_______________________________________________

Hi, Here's a patch for Hexagon Packetizer for review. This patch does not yield any warnings. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonPacketizer.patch URL:

Hi, Here's a Hexagon patch for replacing transfer/copy instructions to combine for review. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. This work is by Arnold Schwaighofer. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name:

Hi, I am trying to print a hex value ( 4111999A for 9.1) for a corresponding floating point number. The routine convertToHexString in APFFloat class only prints in C99 Floating point hexagondecimal constant (eg 1.e00000p3). Without writing my own routine, how do I get to print the hexadecimal representation for a floating point value? Sirish -- Qualcomm Innovation Center, Inc is a member

Here's a Hexagon patch for Hexagon New Value Jump instructions for review. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonNewValueJump.patch URL:

Hi, Given the following in ISDOpcodes.h SETO, // 0 1 1 1 True if ordered (no nans) SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) Is it safe to assume that SETO is not of SETUO? We have support for setuo in the architecture but not seto. Sirish -------------- next part -------------- An HTML attachment was scrubbed...

Hi Craig, protecting the transformation with: if (TLI.isTypeLegal(VT) && TLI.isOperationLegal(ISD::SUB, VT) && TLI.isOperationLegal(ISD::ADD, VT) && TLI.isOperationLegal(ISD::SHL, VT) && TLI.isOperationLegal(ISD::SRA, VT)) { shows the same result. Michael On 22.09.2017 07:19, Craig Topper wrote: > Is VT a legal type on Hexagon?

Hi Sanjay, thanks for this information. I did get a little bit further with the patch. However, Hexagon gives me headaches. I tried to limit the scope of the patch to the BeforeLegalizeTypes phase and Hexagon still reaches the unreachable. Hexagon tries to split or widen a vector type for a node with custom lowering where the unreachable arises from inside TargetLowering::ReplaceNodeResults

Is VT a legal type on Hexagon? It looks like Hexagon may be setting SHL as Custom for every defined vector type. Try adding TLI.isTypeLegal(VT) too. ~Craig On Thu, Sep 21, 2017 at 10:06 PM, Haidl, Michael < michael.haidl at uni-muenster.de> wrote: > Hi Sanjay, > > thanks for this information. I did get a little bit further with the > patch. However, Hexagon gives me headaches.

Hi, I am currently working on a more or less intrusive patch (D37896), which pulls optimizations on multiplications from some back-ends, e.g., (mul x, 2^N + 1) => (add (shl x, N), x) in AArch64, into the DAGCombiner to have this optimization generic on all targets. However, running the LLVM Tests leads to 67 unexpected results. Am 19.09.2017 um 15:58 schrieb Sanjay Patel: > For the

There are multiple problems/questions here: 1. Make sure you've updated trunk to the latest rev before running update_llc_test_checks.py on lea-3.ll. Ie, I would only expect the output you're seeing if you're running the script on a version of that test file before r313631. After that commit, each RUN has its own check prefix, so there should be no conflict opportunity. 2. I

On 03/14/2013 12:51 PM, Anshuman Dasgupta wrote: > I wanted to give everybody a heads-up on upcoming commits for the > Hexagon backend. We will be removing support for older versions of the > Hexagon architecture - specifically Hexagon-v2 and Hexagon-v3. These are > no longer being used by compiler users. Matthew Curtis has committed the > first clang patch to remove driver support

I wanted to give everybody a heads-up on upcoming commits for the Hexagon backend. We will be removing support for older versions of the Hexagon architecture - specifically Hexagon-v2 and Hexagon-v3. These are no longer being used by compiler users. Matthew Curtis has committed the first clang patch to remove driver support for these versions. There will be follow-up patches on the LLVM side

Hi All, I noticed LLVM target independent side is converting an ordered less than "setolt" into unordered greater than "setuge" operation. There are no target hooks to control going from the ordered mode into unordered. I am trying to figure out the best way to support unordered operation on Hexagon. We don't have a single instruction to do unordered operation. So we

Hello, I run into a problem that llvm can't write the correct ELFHeaderEFlags for hexagonv4. The following patch can fix it. Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (revision 265917) +++

Since Jakob had expressed some concerns regarding machine-generated files, I asked him by email about his views on this RFC. Here are the emails that we exchanged in attach. Anyone feel free to jump in via the mailing-list. TIA -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of the Code Aurora Forum -------------- next