similar to: [LLVMdev] Target Dependent Hexagon Packetizer patch

No test cases for a 500k patch? -eric On Apr 18, 2012, at 9:18 PM, Sirish Pande wrote: > Hi, > > Here's a patch for Hexagon Packetizer for review. This patch does not yield any warnings. > > Sirish > > -- > Qualcomm Innovation Center, Inc is a member of Code Aurora Forum > > <HexagonPacketizer.patch>_______________________________________________

Here's a patch that contains Hexagon Test cases. Please review. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonTestCases.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120420/eb32dede/attachment.ksh>

On Apr 20, 2012, at 1:58 PM, Sirish Pande <spande at codeaurora.org> wrote: > Here's a patch that contains Hexagon Test cases. Please review. You can't include these in the patches that they're supposed to go along with? -eric

Sure I can do that. In that case, let me recreate all the patches (along with the test cases) and put up the patches for review. sirish On 4/20/2012 4:16 PM, Eric Christopher wrote: > On Apr 20, 2012, at 1:58 PM, Sirish Pande<spande at codeaurora.org> wrote: > >> Here's a patch that contains Hexagon Test cases. Please review. > You can't include these in the

Hi, Here's a Hexagon patch for replacing transfer/copy instructions to combine for review. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. This work is by Arnold Schwaighofer. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name:

Hi, I am trying to print a hex value ( 4111999A for 9.1) for a corresponding floating point number. The routine convertToHexString in APFFloat class only prints in C99 Floating point hexagondecimal constant (eg 1.e00000p3). Without writing my own routine, how do I get to print the hexadecimal representation for a floating point value? Sirish -- Qualcomm Innovation Center, Inc is a member

Hi, Look at the following code: Look at the following C code seqence: unsigned char mainGtU ( unsigned int i1, unsigned int i2, unsigned char* block) { unsigned char c1, c2; c1 = block[i1]; c2 = block[i2]; if (c1 != c2) return (c1 > c2); i1++; i2++; c1 = block[i1]; c2 = block[i2]; if (c1 != c2) return (c1 > c2); i1++; i2++; .. ..

Hi, Given the following in ISDOpcodes.h SETO, // 0 1 1 1 True if ordered (no nans) SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) Is it safe to assume that SETO is not of SETUO? We have support for setuo in the architecture but not seto. Sirish -------------- next part -------------- An HTML attachment was scrubbed...

Hi, I notice that there exist some classes for VLIW packetizing and other classes for VLIW scheduling. Apparently these classes share something in common. Can someone explain why they should have separate implementation (i.e., in different function passes)? Best regards. -- 杨勇勇 (Yang Yongyong)

Hi Jonas, > It is interesting to find this in the ARM backend, considering your answer. The ARM backend doesn't use the DFA packetizer. It's only used by Hexagon. At this point, there is no plan to address thisin the DFA packetizer since none of the supported targets needthe functionality. Thanks -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,

Hi, I'm trying to get the DFAPacketizer to work for my target but with any instruction I get the 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes out before packeting a single instruction. I have a *GenDFAPacketizer.inc file and my packetizer pass checks that the table is not empty before proceeding. I also have a schedule file with my functional

Jonas, At this point, the DFA packetizer models a simple VLIW architecture and does not accommodate multiple stages. That's the reason for the behavior you're seeing. -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On Behalf Of *Jonas

Hi Ivan, The assertion was happening because I wasn't checking after the first attempt failed. The first packet was failing and so it was ended, and then the packetizer attempted to add it to the next packet without checking for available resources. However this highlights probably the real problem - my packetizer is unable to find resources for the first instruction, or any of my

Hi Anshu, Would there be any interest in extending this algorithm to handling more extensive models, such as VLIW scheduling based on FU's and bundle space... ie handle multiple stages ? I might do it and commit, if there is acceptance and guidance... Jonas ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Tuesday, February 12, 2013 4:47 PM

Hi Sam, On 12/06/2012 15:33, sam wrote: > Hi, > > I'm trying to get the DFAPacketizer to work for my target but with any > instruction I get the > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes > out before packeting a single instruction. Do you reserve some resource without verification? Note that reserveResources() should be

Hi Yang, They have different implementations because they don't do the same thing and don't rely on the same structures. VLIW scheduling works on the SelectionDAG, right after the instruction selection, and it will schedule the DAG but it will not build any packet. The VLIW packetizer has been designed to work with machine instructions, using the ScheduleDAGInstr, and it does build

Hi, I looked a bit through the mail archives, and found this question answered in Oct 2011 (see below). It is interesting to find this in the ARM backend, considering your answer. Can you give more information about for example is this a temporary deficiency in the DFAPacketizer? What is the IIC_iMOVi itinerary doing below? Thanks, Jonas Thu Oct 6 15:11:25 CDT 2011: Hello Hal. > Is there

> Does the instruction that is being added have an itinerary associated with > it? > So I checked again, and it turns out that it does have an itinerary associated with it. However it is a pseudo instruction. Does the packetizer do something special with the pseudo instructions? I didn't see any special code, but I could have missed it. -- R -------------- next part --------------

Hi, I would like to inform the community that I'm releasing the backend for tile64 I developed in the past several months. It can be downloaded from http://pnyf.inf.elte.hu/juhda/projects/tilera/ The version for LLVM 3.1 is a minimalist functioning implementation. Now I am working on utilizing the VLIW packetizer of LLVM, and other improvements are planned for the future. I would be

----- Original Message ----- > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Monday, November 9, 2015 10:09:07 AM > Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries? > > > Anybody? Does anyone at all know how to do it? There is