similar to: [LLVMdev] Announcing 3.1 Release Branch Date!

Le mardi 27 mars 2012 à 14:36 -0700, Bill Wendling a écrit : > IMPORTANT! IMPORTANT! IMPORTANT! > [...] > By the way, we are looking for ARM testers. There was a lot of interest in the 3.0 release for an ARM release. We will try to do one this release on a trial basis. We are looking for ARMv7 cortex-a8 and cortex-a9 on Linux. If you are interested, I can upload the current trunk

> By the way, we are looking for ARM testers. There was a lot of interest in the 3.0 release for an ARM release. We will try to do one this release on a trial basis. We are looking for ARMv7 cortex-a8 and cortex-a9 on Linux. We have two pandard board (ARMv7 cortex-a9) and perhaps one ARMv6 4-cores board. Do we do a native compile or cross compile for the ARM platform? Regards, chenwj --

On Mar 29, 2012, at 2:46 AM, 陳韋任 <chenwj at iis.sinica.edu.tw> wrote: >> By the way, we are looking for ARM testers. There was a lot of interest in the 3.0 release for an ARM release. We will try to do one this release on a trial basis. We are looking for ARMv7 cortex-a8 and cortex-a9 on Linux. > > We have two pandard board (ARMv7 cortex-a9) and perhaps one ARMv6 > 4-cores

On Apr 24, 2012, at 8:05 PM, 陳韋任 wrote: > Hi Bill, > > I forgot to do Phase2/Phase3 build. Here is the Phase3 regression test > result, > > http://people.cs.nctu.edu.tw/~chenwj/tmp/phase3-regression-test.txt > > Most LLVM failures are gone. As for ExecutionEngine, I guess ARM JIT is > not at a good shape at this moment, right? Perhaps we should focus on Clang >

Hi Bill, Here is the summary of Clang failures (part of). Clang :: CXX/conv/conv.prom/p2.cpp chandlerc doubts the test itself is fulfill the C++ standard. Although "-fshort-wchar" makes the error disappered, chandlerc think it's not the correct solution. Perhaps it's test bug not clang's. Clang :: CXX/special/class.copy/p15-inclass.cpp Clang

Hello, I asked here for kind of reference GCC version which LLVM development team is using for *native* testing on ARM hardware. (no cross compilation!) last week or so. I've been curious myself how the situation looks and so I tested LLVM 2.9 as a reference point and LLVM HEAD as of June 29 on ARMv7 (two boards with two different Ubuntu versions) compiled by GCC 4.3.4, 4.4.1, 4.4.5,

Update: > Clang :: CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp > > Seems to be difference between ARM and Intel C++ ABI, but I leave it to > James to comment. Use "-triple x86_64-none-linux-gnu" makes this test pass. Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.)

The following failures are consistent on buildbot (and my local box). The Clang one I think it's assuming an Intel box, the other two look like the FileCheck are not good enough. http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/4305 Clang :: CodeGen/compound-assign-overflow.c LLVM :: Transforms/LoopStrengthReduce/post-inc-icmpzero.ll LLVM ::

Hi, - Cortex-A8 needs a specific instruction scheduler as dual issue forces you to interleave some instructions to allow to run two instructions in the same cycle for the best performance (Cortex-A9 is out-of-order so dual issue is not an issue (!) for performance). - Cortex-A8/A9 have several useful new instructions : for instance, bit operations like bitfield insertion/extraction or having

My goal is to have Cortex-A9 support complete in far less than three months. I've recently gotten some additional help toward that goal, so the pace should pick up soon. As far as compiler texts, there are many newer texts to recommend as just about all the major optimization passes are done differently after SSA-form appeared in about 1991. However, for adding Cortex-A8 support, I don't

On Apr 3, 2013, at 2:07 AM, Renato Golin <renato.golin at linaro.org> wrote: > On 1 April 2013 22:05, Bill Wendling <wendling at apple.com> wrote: > We would like to support ARM again. > > Hi Bill, > > Glad you asked! ;) > > I'm getting the test-suite bot green (a few minor tweaks and we're good) and that should get us well ahead of what we've

Sandeep Patel wrote: > My goal is to have Cortex-A9 support complete in far less than three > months. I've recently gotten some additional help toward that goal, so > the pace should pick up soon. > > As far as compiler texts, there are many newer texts to recommend as > just about all the major optimization passes are done differently > after SSA-form appeared in about

Hi Renato, It's definitively not A15. Can this be the case that NEON units for cortex-A9 support it but isn't documented/recommended ? And as mentioned before code is working ! Seb > -----Original Message----- > From: rengolin at gmail.com [mailto:rengolin at gmail.com] On Behalf Of > Renato Golin > Sent: Friday, November 09, 2012 6:27 PM > To: Sebastien DELDON-GNB >

Hi Bastien, Weird gcc is generating fma for my platform STEricsson Novathor with Linaro, code works. It also works when I use LLVM to generate fma (using llc -mtriple=armv7-eabi). Maybe someone from ARM can answer the question ? Seb From: JF Bastien [mailto:jfb at google.com] Sent: Friday, November 09, 2012 5:36 PM To: Sebastien DELDON-GNB Cc: Anitha Boyapati; llvmdev at cs.uiuc.edu Subject:

Christophe Avoinne wrote: > Hi, > > - Cortex-A8 needs a specific instruction scheduler as dual issue forces > you to interleave some instructions to allow to run two instructions in > the same cycle for the best performance (Cortex-A9 is out-of-order so > dual issue is not an issue (!) for performance). > - Cortex-A8/A9 have several useful new instructions : for instance,

Hi, Hi, I was going through Code of LLVM instruction code generation for ARM. I came across VMLA instruction hazards (Floating point multiply and accumulate). I was comparing assembly code emitted by LLVM and GCC, where i saw that GCC was happily using VMLA instruction for floating point while LLVM never used it, instead it used a pair of VMUL and VADD instruction. I wanted to know if there is

Hi Anitha, Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable fused mac generation for me. I would like just to understand why -mtriple=armv7-eabi enables it while -mcpu=cortex-a9 seems to disable it ? Seb > -----Original Message----- > From: Anitha Boyapati [mailto:anitha.boyapati at gmail.com] > Sent: Thursday, November 08, 2012 10:22 AM > To: Sebastien

On Mar 29, 2012, at 12:57 PM, Jim Grosbach <grosbach at apple.com> wrote: > On Mar 29, 2012, at 2:46 AM, 陳韋任 <chenwj at iis.sinica.edu.tw> wrote: > >>> By the way, we are looking for ARM testers. There was a lot of interest in the 3.0 release for an ARM release. We will try to do one this release on a trial basis. We are looking for ARMv7 cortex-a8 and cortex-a9 on

cat /proc/cpuinfo ? Are you sure it's generating VFMA and not VMLA? On Fri, Nov 9, 2012 at 9:35 AM, Sebastien DELDON-GNB < sebastien.deldon at st.com> wrote: > Hi Renato, > > It's definitively not A15. Can this be the case that NEON units for > cortex-A9 support it but isn't documented/recommended ? > And as mentioned before code is working ! > > Seb >

Hi Sebastien, ARMv7-M has VFMA and LLVM's "triple" is far from perfect. Wikipedia tells me NovaThor can also be A15, or STE could have cramped a VFPv4 in it? ;) Or possibly, your code never branches into the VFMA. Many things could be happening, but usually, VFMA shouldn't be generated for A9. A GCC bug, maybe? On 9 November 2012 16:51, Sebastien DELDON-GNB