similar to: [LLVMdev] DAG type Legalizer bug?

Hey, I’ve been working on custom lowering ISD::UMUL_LOHI and ISD::SMUL_LOHI. Our target has some legal vector types but no support for these so would like to mark them as Expand. This yields “Cannot unroll a vector with multiple results!” from the default case in VectorLegalizer::Expand. Hence custom lowering. All the types are legal at this stage. I would appreciate some clarification on

Centralize capability related functions into several new functions and put PCI resource definitions into an enum. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at

Centralize capability related functions into several new functions and put PCI resource definitions into an enum. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at

[PATCH 1/4] PCI: export pci_read_base and add pci_update_base Export pci_read_base; add pci_update_base to for PCI BAR update. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/probe.c | 25 ++++++++-------- drivers/pci/setup-res.c | 74 +++++++++++++++++++++++++++-------------------- include/linux/pci.h |

[PATCH 1/4] PCI: export pci_read_base and add pci_update_base Export pci_read_base; add pci_update_base to for PCI BAR update. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/probe.c | 25 ++++++++-------- drivers/pci/setup-res.c | 74 +++++++++++++++++++++++++++-------------------- include/linux/pci.h |

[PATCH 1/4] PCI: export pci_read_base and add pci_update_base Export pci_read_base; add pci_update_base to for PCI BAR update. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/probe.c | 25 ++++++++-------- drivers/pci/setup-res.c | 74 +++++++++++++++++++++++++++-------------------- include/linux/pci.h |

Some basic changes to allocation bus range, MMIO resource for SR-IOV device. And add new sysfs entry to hotplug core to pass parameter to a slot, which will be used by SR-IOV code. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/bus.c | 63 +++++++++++++-------------

Some basic changes to allocation bus range, MMIO resource for SR-IOV device. And add new sysfs entry to hotplug core to pass parameter to a slot, which will be used by SR-IOV code. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/bus.c | 63 +++++++++++++-------------

Some basic changes to allocation bus range, MMIO resource for SR-IOV device. And add new sysfs entry to hotplug core to pass parameter to a slot, which will be used by SR-IOV code. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/bus.c | 63 +++++++++++++-------------

(resending with smaller attachement) Segfault in EE->getPointerToFunction. I think it's blown the stack, gdb reports a never ending backtrace (below). I generate llvm assembly and parse/verify OK. Attached is the assembly. It is the smallest example generated that causes the segfault. If this EE uses a recursive function (??), it seems an inherent limitation in how big llvm functions

Segfault in EE->getPointerToFunction. I think it's blown the stack, gdb reports a never ending backtrace (below). I generate llvm assembly and parse/verify OK. Attached is the assembly. It is the smallest example generated that causes the segfault. If this EE uses a recursive function (??), it seems an inherent limitation in how big llvm functions can be. Simon. gdb backtrace: #0

Add Single Root I/O Virtualization (SR-IOV) support. Signed-off-by: Yu Zhao <yu.zhao@intel.com> diff -r 040046b91eb7 -r 75504b97c0ab drivers/pci/Kconfig --- a/drivers/pci/Kconfig Sat Sep 27 01:25:31 2008 -0400 +++ b/drivers/pci/Kconfig Sat Sep 27 01:27:01 2008 -0400 @@ -27,3 +27,14 @@ When in doubt, say N. +config PCI_IOV + bool "PCI SR-IOV support"

Hi Simon, You're probably right. LLVM's instruction selector is recursive so it can run out of stack space. Select_store used to have enormous stack frame (thanks to some gcc issues), we had to do all kinds of tricks to get it under control. I just took a look at it, it's around 0.7k. It used to be around 20k on x86 Mac OS X. It's also possible that it has gotten into a

Support SR-IOV capability. By default, this feature is not enabled and the SR-IOV device behaves as traditional PCI device. After it's enabled, each Virtual Function's PCI configuration space can be accessed using its own Bus, Device and Function Number (Routing ID). Each Virtual Function also has PCI Memory Space, which is used to map its own register set. Signed-off-by: Yu Zhao

Support SR-IOV capability. By default, this feature is not enabled and the SR-IOV device behaves as traditional PCI device. After it's enabled, each Virtual Function's PCI configuration space can be accessed using its own Bus, Device and Function Number (Routing ID). Each Virtual Function also has PCI Memory Space, which is used to map its own register set. Signed-off-by: Yu Zhao

Support SR-IOV capability. By default, this feature is not enabled and the SR-IOV device behaves as traditional PCI device. After it's enabled, each Virtual Function's PCI configuration space can be accessed using its own Bus, Device and Function Number (Routing ID). Each Virtual Function also has PCI Memory Space, which is used to map its own register set. Signed-off-by: Yu Zhao

Reserve bus range for SR-IOV at device scanning stage. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at cisco.com> Cc: Greg KH <greg at kroah.com>

Add Single Root I/O Virtualization (SR-IOV) support. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at cisco.com> Cc: Greg KH <greg at kroah.com>

Add Single Root I/O Virtualization (SR-IOV) support. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at cisco.com> Cc: Greg KH <greg at kroah.com>

Hello, Tim, Thank you for your advice. Indeed, the problem with "LLVM ERROR: Cannot select" was a false predicate that should have been true. I solved the problem by simply making the C++ function implementing the TableGen predicate used in my store instruction (very similar to the selectIntAddrMSA predicate from the Mips back end) return true instead of false. But