similar to: [LLVMdev] Expand vector type

Displaying 20 results from an estimated 800 matches similar to: "[LLVMdev] Expand vector type"

2012 Feb 29
2
[LLVMdev] Expand vector type
James, Thanks for your response. I'm working in LLVM 2.7 (I know, it's old) and the default behavior is already promote. This means that for example a call to DAGTypeLegalizer::getTypeAction(v3i32) in my case and I presume in ARM NEON returns TypeWidenVector. From here legalization calls WidenVectorOperand() to process the STORE node and follows the call chain I have on my original email
2012 Feb 29
0
[LLVMdev] Expand vector type
Hi, * Is there a way to setup LLVM to automatically convert vec3s to vec4s? Yes, if you specify v3i16 and friends as "promote" instead of "legal", llvm will promote it to a v4i16. The ARM NEON backend does this already. I'm surprised you haven't got this happening already as you mention that LLVM widens your loads to 4-element vectors. (this should happen during
2012 Mar 05
0
[LLVMdev] Expand vector type
I still haven't received any feedback on me adding support for widening of stores. Is there interest? Thanks, Javier From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Martinez, Javier E Sent: Wednesday, February 29, 2012 11:35 AM To: James Molloy; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Expand vector type James, Thanks for your response.
2012 Mar 05
1
[LLVMdev] Expand vector type
Hi Javier, On 05/03/12 18:10, Martinez, Javier E wrote: > I still haven’t received any feedback on me adding support for widening of > stores. Is there interest? did you try LLVM 3.0? Ciao, Duncan. > > Thanks, > > Javier > > *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *Martinez, Javier E > *Sent:* Wednesday,
2019 Feb 01
2
[RFC] Vector Predication
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay <programmerjake at gmail.com> wrote: > > We're in-progress designing a RISC-V extension (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) that would have variable-length vectors of short vectors (1 to 4): > <VL x <4 x
2019 Feb 01
3
[RFC] Vector Predication
On Fri, Feb 1, 2019 at 1:19 AM Bruce Hoult <brucehoult at sifive.com> wrote: > On Thu, Jan 31, 2019 at 11:53 PM Luke Kenneth Casson Leighton via > llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > --- > > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 > > > > On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay
2012 Nov 08
5
map two names into one
Thanks. Yes. Your approach can identify: Glaxy ace S 5830 and S 5830 Glaxy ace But you can not identify using same program: Iphone 4S 16 G Iphone 4S 16G How should I solve both in same time. Kind regards,Tammy [[alternative HTML version deleted]]
2013 Sep 05
2
binary symmetric matrix combination
Hi, May be this helps: m1<- as.matrix(read.table(text=" y1 g24 y1 0 1 g24 1 0 ",sep="",header=TRUE)) m2<-as.matrix(read.table(text="y1 c1 c2 l17 ?y1 0 1 1 1 ?c1 1 0 1 1 ?c2 1 1 0 1 ?l17 1 1 1 0",sep="",header=TRUE)) m3<- as.matrix(read.table(text="y1 h4??? s2???? s30 ?y1 0 1 1 1 ?h4 1 0 1 1 ?s2 1 1 0 1 ?s30 1 1 1
2012 Aug 24
6
updating elements of a vector sequentially - is there a faster way?
I would like to know whether there is a faster way to do the below operation (updating vec1). My objective is to update the elements of a vector (vec1), where a particular element i is dependent on the previous one. I need to do this on vectors that are 1 million or longer and need to repeat that process several hundred times. The for loop works but is slow. If there is a faster way, please let
2019 Jan 31
6
[RFC] Vector Predication
Hi, There is now an RFC for a roadmap to native vector predication support in LLVM and a prototype implementation:   https://reviews.llvm.org/D57504 The prototype demonstrates: -  Predicated vector intrinsics with an explicit mask and vector length parameter on IR level. -  First-class predicated SDNodes on ISel level. Mask and vector length are value operands. -  An incremental strategy
2012 Apr 05
0
[LLVMdev] Difference between 2.9 and 3.0 in intel ASM printer
Hi, I'm almost there with my Yasm printer, however, I've stumbled upon this. Using this: ; ModuleID = 'data.u' %window = type { %visobj, %vec2, %vec2, %vec2, %string, %color, i32, i32, %string, %string, %string, i1, i1, i1, i1, i1, i1, i32, i8* } %visobj = type { %object, i1, i1, i1, i1, %color, %vec4, %vec4, %vec4, %vec4, i32, %mat4, %mat4, %mat4, %mat4, %material*,
2019 Feb 01
3
[RFC] Vector Predication
Hi, On 1/31/19 11:20 PM, Jacob Lifshay wrote: > We're in-progress designing a RISC-V extension > (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) > that would have variable-length vectors of short vectors (1 to 4): > <VL x <4 x float>> > where each predicate bit masks out a whole short vector. We're using > this extension
2011 Aug 12
1
[LLVMdev] Using sret AND thiscall calling convention
Hi all, I am trying to generate LLVM IR that calls an external C++ function returning a structure by copy: vec3 vec3::Cross(const vec3& iV) const; Here is the LLVM IR that I am generating for win32 ABI, which says that the first parameter should be a pointer to the return value: %vec3 = type <{ float, float, float }> define void @CPP_Return_Struct(%vec3* %v1, %vec3* %v2) inlinehint
2008 Nov 18
1
[LLVMdev] Do I need to add new intrinsic functions for the OpenGL shading language swizzle?
OpenGL shading language (GLSL) is like a C subset language, but it contains some special features, ex: native vector type & swizzle. In GLSL, you can declare vector types: void main() { vec4 a; vec3 b; vec2 c; } You can access the element of vector by using .xyzw, it means the 1st, 2nd, 3rd, 4th element of the vector are x, y, z, w. Ex: void main() { float f; vec4 a = vec4(1.0,
2011 Aug 12
1
[LLVMdev] Using sret AND thiscall calling convention
On Fri, Aug 12, 2011 at 1:11 AM, Damien Gleizes <gleizesd at gmail.com> wrote: > > Hi all, > > I am trying to generate LLVM IR that calls an external C++ function > returning a structure by copy: > vec3 vec3::Cross(const vec3& iV) const; > > Here is the LLVM IR that I am generating for win32 ABI, which says that the > first parameter should be a pointer to the
2014 Dec 07
3
[LLVMdev] NEON intrinsics preventing redundant load optimization?
Hi all, I’m not sure if this is the right list, so apologies if not. Doing some profiling I noticed some of my hand-tuned matrix multiply code with NEON intrinsics was much slower through a C++ template wrapper vs calling the intrinsics function directly. It turned out clang/LLVM was unable to eliminate a temporary even though the case seemed quite straightforward. Unfortunately any loads
2014 Aug 11
2
[LLVMdev] tablegen pattern
Hi Guys, I have a taget instruction which take a vec4 and returns a vec4.( say instruction “vec4:$dst mod( vec4:$src)" ) And I want to use it to match i an ir instruction/intrinsic function( say " float:$dst llvm.irmod( vec4:$src)" which takes a vec4, output a float. I think the procedure is: when I see the intrinsic llvm.irmod, I need to call "extractlt(
2010 Aug 24
3
multiple assignments ?
Simple one, have read and googled, still no luck! I want to create several empty vectors all of the same length. I would like multiple empty vectors (vec1, vec2, vec3) and want to create them all in one line. I've tried vec1,vec2,vec3 <- vector(length=5) and c(vec1,vec2,vec3) <- vector(length=5) and several other attempts but nothing seems to work ... suggestions? Thanks Jim
2012 Aug 27
1
[LLVMdev] PROPOSAL: IR representation of detailed struct assignment information
On Aug 27, 2012, at 11:37 AM, gohman at apple.com wrote: > On Aug 24, 2012, at 5:56 PM, Alex Rosenberg <alexr at leftfield.org> wrote: > > > If we can also describe the alignment padding inserted at the end of a struct when it is placed in an array, then we can improve the current LoopIdiom pass to build more memcpys. I would think that would be attached to the struct
2015 May 04
2
[LLVMdev] Incorrect code generated for arm64
Hi all, I’ve narrowed down a problem in my code to the following test case: - - - - typedef struct {float v[2];} vec2; typedef struct {float v[3];} vec3; vec2 getVec2(); vec3 getVec3() { vec2 myVec = getVec2(); vec3 res; res.v[0] = myVec.v[0]; res.v[1] = myVec.v[1]; res.v[2] = 1; return res; } - - - - Compiling this with any level of optimization for arm64 gives incorrect code,