similar to: [LLVMdev] Possible fix for Bug 1388 - CPY instruction emitted on < ARMv6T

Hi Gordon, You're talking about Thumb mode code here, right? As I understand it, the ARM mode MOV instruction is valid for everything ARMv4 and up. (nit picky side note: CPY is an obsolete mnemonic as of the introduction of unified syntax) Assuming so, using a high register causes headaches, as R8+ are call preserved registers, and the Thumb push/pop instructions can't reference them.

what do you mean by "more optimal instructions" ? -omer On Wed, Nov 16, 2011 at 1:28 AM, Joe Abbey <jabbey at arxan.com> wrote: > I've done a first pass over the past 6 months of changes and some notable > things stood out: > > * The ARM backend has reworked Set Jump Long Jump EH Lowering. > * The ARM backend includes improved support for Cortex-M > *

Hi all. I'm looking for some way to do code analysis with LLVM. Can someone please give me a hint, if it is possible to query an MCInst for what are input operands and what are output operands? Small example. Consider we have an instruction: str r1, [sp, #8] Being mapped into MCInst instance it has the following operands: <MCOperand Reg:61> <-- maps to reg r1

Hi, I'm fairly new at poking around in llvm internals so if you find misconceptions / problems with the below let me know, this is just how I've understood this so far. When doing a build which uses functionality from LinkModules to combine bitcode from different versions of LLVM, or between LLVM-GCC (I know) and Clang, I've noticed that multiple warnings which sometimes seem

Dear All, LLVMdev just got SPAM from roger83 at hotmail.co.uk. Please do not click on any of the links in that email. I've unsubscribed and banned this email address from llvmdev. Roger Roger is Banned Banned. -- John T.

Hi, I'm trying to emit a conditional move in the ARM backend for a custom intrinsic. Basically, I want to emit the following the following instruction sequence: cmp r0, r1 moveq r2, #1 To implement this, I first emit a compare instruction and then I'm trying to emit the conditional move, which is failing. BuildMI(&MBB, DL, TII->get(ARM::CMPrr))

I've done a first pass over the past 6 months of changes and some notable things stood out: * The ARM backend has reworked Set Jump Long Jump EH Lowering. * The ARM backend includes improved support for Cortex-M * The ARM backend adds parsing and encoding ARM/Thumb/Thumb2 assembly There are also many many code generation improvements which select more optimal instructions. Those seemed

On Sat, Sep 4, 2010 at 1:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > >> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer

On 04/12/2012 06:29, Michael Spencer wrote: > On Mon, Dec 3, 2012 at 8:08 PM, Gordon Keiser <gkeiser at arxan.com> wrote: >> As an update to this: >> http://connect.microsoft.com/VisualStudio/feedback/details/769222/cl-exe-ice-when-building-llvm-trunk-at-o2 >> >> Microsoft has reproduced the ICE, given a workaround, and is planning a fix for a future MSVC release.

Cool, I'll file a bug tomorrow at work and add you to the CC list. Thanks! Gordon Keiser Software Development Engineer Arxan Technologies gkeiser at arxan.com www.arxan.com  Protecting the App EconomyT  > -----Original Message----- > From: Eric Christopher [mailto:echristo at gmail.com] > Sent: Tuesday, August 20, 2013 9:47 PM > To: Gordon Keiser > Cc: llvmdev at

All, ARM LLVM afficianados: I'm trying to understand how LiveVariables computes liveness for CPSR. In particular, I would like to tell whether a particular instruction is a use/kill/def for doing some within block liveness checking I need. Thanks in advance, David -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, I was wondering if there was any way to return an i1 type (or something that llvm would accept as one, internally) from a C function compiled with llvm-gcc. My thought from searching around was that it might take rewriting (or at least writing a wrapper to %trunc the result) in assembly. I'm fairly new to LLVM so I may have missed something important. Any thoughts ? Thanks much,

On Tue, 16 Jun 2020 at 15:47, Tim Northover <t.p.northover at gmail.com> wrote: > > On Tue, 16 Jun 2020 at 10:23, Prathamesh Kulkarni via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > (b) Modifies RegisterCoalescer::reMaterializeTrivialDef and > > TargetInstrInfo::isReallyTriviallyReMaterializableGeneric to check > > for single live def, instead of

Hi, Running 9.2-PRERELEASE #19 r253313 I got the following panic Fatal trap 12: page fault while in kernel mode cpuid = 22; apic id = 46 fault virtual address = 0xffffff827ebca30c fault code = supervisor read data, page not present instruction pointer = 0x20:0xffffffff81983055 stack pointer = 0x28:0xffffffcf75bd60a0 frame pointer = 0x28:0xffffffcf75bd68f0

> On Behalf Of Nicholas Chapman > > On 04/12/2012 06:29, Michael Spencer wrote: > > On Mon, Dec 3, 2012 at 8:08 PM, Gordon Keiser <gkeiser at arxan.com> > wrote: > >> As an update to this: > >> http://connect.microsoft.com/VisualStudio/feedback/details/769222/cl- > >> exe-ice-when-building-llvm-trunk-at-o2 > >> > >> Microsoft

On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer code, but since LLVM is so nearer to the optimal code sequence i wanted to reach it. In LLVM, copies are

LGTM On Wed, Aug 21, 2013 at 1:51 PM, Logan Chien <tzuhsiang.chien at gmail.com> wrote: > Hi, > > I have created a workaround to deal with the PIC function call. With this > patch, the FastISel will switch back to DAG lowering mechanism if (1) there > is a function call in the basic block and (2) the relocation model is PIC. > Please have a look. Hoping the patch will

Ok, Scratching the surface this morning on Bug 1388. Happy to find that CCR has already been defined in ARMRegisterInfo.td However all uses in the instruction info tablegen files indicate that a two-value operand can't be used where a dag node expects two operands. // FIXME: should be able to write a pattern for ARMBrcond, but can't use // a two-value operand where a dag node

Evan & llvmdev, I'm seeing a case where ARM Load/Store optimizer is breaking code. I have not had any luck trying to come up with a minimal example; it is breaking in our stage 2 LLVM build. But here's what I'm seeing in the debug output: # Before ARMLoadStoreOptimizer: BB#21: derived from LLVM BB %cond.end Live Ins: %LR %R0 %R1 %R7 %R10 %R11 Predecessors according to

As an update to this: http://connect.microsoft.com/VisualStudio/feedback/details/769222/cl-exe-ice-when-building-llvm-trunk-at-o2 Microsoft has reproduced the ICE, given a workaround, and is planning a fix for a future MSVC release. I know not a lot of people are building with VS, but it's nice to know. The workaround involves marking a single function with attribute((noinline)) and is