similar to: [LLVMdev] Stop MachineCSE on certain instructions

If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. Evan On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated instruction bundle (3 > instructions) that has to be executed like a single block (meaning: if > the first instruction

Hi Evan. The hasSideEffects method I believe operates only on Inline Assembly (IA) blocks. What if such a sequence is not part of IA? Thanks. Girish. If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. > >Evan > >On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > >> Hello, >>

Hi Johannes, You may be interested in the (very) recently added explicit instruction bundle support. For an example of their usage, have a look at the ARM backend's IT-block (Thumb2 predication support) pass, which uses them to tie instructions together. -Jim On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM

Hi, Jim. In my case the target (Tilera) doesn't have a full 32-bit mult operation and to do so it has to accumulate results from three 16-bit mults, by retaining operands and the result across in the same registers. However the ISel DAG thinks its a CSE case. Please note this is not a MAdd/MSub triad. How could I do this by defining such a sequence or the pattern in the .def file itself for

Hi Girish, Sorry, but I'm afraid I don't understand your question. Can you elaborate a bit? -Jim On Dec 19, 2011, at 9:12 PM, girish gulawani wrote: > > Hello Jim. > Just out of curiosity, won't such mechanism work via the patterns from instructions defs? > > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: Johannes

Ah, OK. I think I understand much better now. Thanks! You shouldn't need bundles for that sort of thing. A custom lowering or a fancy pattern should be sufficient, depending on the details of how your target is defined. For patterns, looks at the various targets use of the Pat<>, Pattern<>, ComplexPattern<> and related classes in the .td files. For examples of custom

Hi Jim. I'm doing custom lowering but here I have a very basic issue and the situation is like this - [Original Op] Mul Dest, Src1, Src2 [Expanded from EmitInstrWithCustomInserter] Step1 Dest, Src1, Src2    <=== BuildMI(..., Step1, Dest).addReg(Src1).addReg(Src2) Step2 Dest, Src1, Src2    <=== BuildMI(..., Step2, Dest).addReg(Src1).addReg(Src2) Step3 Dest, Src2, Src1    <===

Hi, My target has a special configuration register that many instructions read implicitly, configuring for example if an add instruction should saturate at over/underflow or not. Now, I have a problem where the MachineCSE removes a setting of this configuration register in a basic block, because MachineCSE::isPhysDefTriviallyDead can't find any uses of it in the basic block where

On 05/23/2018 11:06 AM, Hubert Tong via llvm-dev wrote: > Hi Ulrich, > > I am interested in knowing if the current proposals also take into > account the FP_CONTRACT pragma We should already do this (we turn relevant operations into the @llvm.fmuladd. when FP_CONTRACT is set to on during IR generation). > and the ability to implement options that imply a specific value for >

Am 07.10.2010 um 19:50 schrieb Chris Lattner: > > On Oct 6, 2010, at 6:16 PM, Gabor Greif wrote: > >> Hi all, >> >> I am slowly working on a SwitchInst optimizer (http://llvm.org/ >> PR8125) >> and now I am running into a deficiency of the x86 >> peephole optimizer (or jump-threader?). Here is what I get: >> >> >> andl $3,

Hello everyone, I wanted to attach a node without affecting the present nodes in any way. I tried to use MVT::Glue for that but I think I'm missing something as I could not achieve the below state. LUI LUI | | ADDI ----GLUE---- ADDI | store I've few question about this and Glue node in general, I'll be happy to get some help on

On Oct 13, 2010, at 11:22 AM, Gabor Greif wrote: > Hi Chris, > > I had a look into MachineCSE, but it looks like MBB-oriented. > The above problem is an inter-block one. Also MCSE seems > to perform value numbering on virtual/physical registers, which > does not map very well to status register bits that are implicitly > defined. > Any chance to recast this issue as a

On 13/09/11 17:40, Devang Patel wrote: > On Sep 13, 2011, at 4:01 AM, Kyriakos Georgiou wrote: >> I've been investigating a case with the XCore target (which doesn't use >> FastISel) where the DWARF line number emitted at -O0 results in the xgdb >> visiting source lines in an unexpected order. I've tracked down the >> problem to the handling of DebugLocs in

On Wed, May 23, 2018 at 12:19 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > On 05/23/2018 11:06 AM, Hubert Tong via llvm-dev wrote: > > Hi Ulrich, > > I am interested in knowing if the current proposals also take into account > the FP_CONTRACT pragma > > > We should already do this (we turn relevant operations into the > @llvm.fmuladd. when FP_CONTRACT is

Hi, I found that in some cases llvm generates duplicate loads of double constants, e.g. $ cat t.c double f(double* p, int n) { double s = 0; if (n) s += *p; return s; } $ clang -S -O3 t.c -o - ... f: # @f .cfi_startproc # BB#0: xorps %xmm0, %xmm0 testl %esi, %esi je .LBB0_2 # BB#1: xorps

Hi all, Is there any existing pass that performs fast local common subexpression elimination? The reason I'm asking is because global common subexpression elimination (GVN or GVN-PRE) is too slow for my JIT purposes, but I see lots of value in local CSE. Thanks, Nicolas -------------- next part -------------- An HTML attachment was scrubbed... URL:

On 21 August 2017 at 11:53, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > One thing to be aware of with this is that (IIRC) tablegen uses the pattern to infer things about the pattern. One example I vaguely remember is that an empty pattern would result in the same effect as hasSideEffects=1 and I think there were others. Thanks for the note - excellent point. Looking at

Hello Dev, I have a very simple testcase, which shows strange difference between LLVM and GCC. Does anyone know which optimization pass removes the condition? Thanks! C code: extern void bar(int, int); void foo(int a) { int b, d; if (a > 114) { b = a * 58; } else { d = a * 51; } bar(b, d); } clang.7.0.1 -O2, LLVM generated assembly: 0: 6b c7 3a

On 19.03.2016 16:25, Mehdi Amini wrote: > Hi, > > Can you elaborate what is the impact at the IR level? > If the point is just about how you lower for you target, why are you needing an IR level attribute? You backend if free to specialize the lowering for any intrinsic regardless the IR level attributes. As I explained in my reply to Philip, what I really need is a way to get