similar to: [LLVMdev] Scheduler information

Hi list, Could anyone help me to roughly understand the internal data dependecy structure used by the scheduler ? As far as I can see in /lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp, SUnit nodes are created to wrap SDNodes with scheduling related information and SDeps represent all kind of dependencies between them. Nevertheless, I cannot figure out the graphical form of such structure. For

Andy, I traced my problem to this point: In ScheduleDAGInstrs.cpp we have the following function: /// addVRegDefDeps - Add register output and data dependencies from this SUnit /// to instructions that occur later in the same scheduling region if they read /// from or write to the virtual register defined at OperIdx. /// /// TODO: Hoist loop induction variable increments. This has to be ///

Hello, Still trying to write a custom scheduler, I stumbled accross a highly suspicious code in all schedulers. In both ScheduleDAGFast.cpp and ScheduleDAGRRList.cpp, one can find this piece of code: SUnit *CopyFromSU = CreateNewSUnit(NULL); and then in the same files: SUnit *CreateNewSUnit(SDNode *N) { [...] SUnit *NewNode = NewSUnit(N); And finally in ScheduleDAGSDNodes.cpp: SUnit

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > >

On Apr 20, 2012, at 10:31 AM, dag at cray.com wrote: > I'd like to begin a project to rework the scheduler to address some > problems we've discovered on this end. The goal is to get a more > configurable/flexible scheduler while simplifying maintenance by > separating policy from implementation to get independent and > interchangeable parts. > > This is going to be

Andy, et al., In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this: if (!ExitSU.isPred(SU)) // Push store's up a bit to avoid them getting in between cmp // and branches. ExitSU.addPred(SDep(SU, SDep::Artificial)); This code does not seem to be in any way specific to compares; and in any case, at least on the PPC A2, scheduling stores in

Andy, Thanks for reply. I was able to trace the problem to the MI DAG dep constructor. See this: SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 # preds left : 0 # succs left : 0 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;

On Jan 17, 2014, at 4:03 PM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 17, 2014, at 3:54 PM, Hal Finkel <hfinkel at anl.gov> wrote: > >> Andy, et al., >> >> In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this: >> >> if (!ExitSU.isPred(SU)) >> // Push store's up a bit to avoid them

Andrew Trick <atrick at apple.com> writes: > We plan to move to the MachineScheduler by 3.2. The structure is: How hard will this be to backport to 3.1? Has woprk on this started yet? > ScheduleDAG: Abstract DAG of SUnits and SDeps > | > v > ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI > Delimit the current

Andy, You are probably right here - look at this - before phi elimination this code looks much more sane: # *** IR Dump After Live Variable Analysis ***: # Machine code for function push: SSA Function Live Outs: %R0 BB#0: derived from LLVM BB %entry %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4

Hi, See below I reply your message for <https://stat.ethz.ch/pipermail/r-help/2008-April/160966.html>[R] predict.glm & newdata posted on Fri Apr 4 21:02:24 CEST 2008 You say it ##works fine but it does not: if you look at the length of yhat2, you will find 100 and not 200 as expected. In fact predict(reg1, data=x2) gives the same results as predict(reg1). So I am still looking for

Hi all, In several of our tests, I have noticed that the register allocator allocates to virtual registers in a different order when compiling with the clang option -g. Before entering the register allocator, the code is identical when compiling with and without -g (with the exception of " DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index

Hello, I'm writing a backend for an architecture that only has LOAD Instructions that first copy the old value of the target register in another register and after that load the provided value into the register. Example of an addition: load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a into reg1 load b, reg1; // -> copies old value of reg1 in reg2 and loads

> On Feb 2, 2017, at 8:20 AM, David Blaikie <dblaikie at gmail.com> wrote: > > The goal/intent is that debug info does not affect code generation. There are (many?) bugs. I think Apple folks (cc'd Adrian) may be looking at this a bit recently, not sure. > > The fixes aren't usually too invasive (usually involve something counting instructions where it needs to skip

Hi list, in our LLVM-based-project we are writing a backend for our processor. The architecture is a quite straight-forward RISC, but it does not have hardware interlocks, i.e. data hazards involving memory access must be resolved by the compiler, either by scheduling unrelated instructions or by inserting NOOPs into the load delay slots: ---- For example, code which looks like that: load

> On Feb 2, 2017, at 8:20 AM, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > The goal/intent is that debug info does not affect code generation. There are (many?) bugs. I think Apple folks (cc'd Adrian) may be looking at this a bit recently, not sure. > > The fixes aren't usually too invasive (usually involve something counting instructions where

On Jan 19, 2009, at 9:17 AM, Patrick Boettcher wrote: > Hi list, > > in our LLVM-based-project we are writing a backend for our > processor. The > architecture is a quite straight-forward RISC, but it does not have > hardware interlocks, i.e. data hazards involving memory access must be > resolved by the compiler, either by scheduling unrelated > instructions or >

Hi folks, I'm running into this weird issue where the register spills appear to be missing for an "if" block for some reason. For example, the original if/else blocks: --- if reg0 // storeRegToStackSlot for reg1 // do something - missing a load for reg1? else // storeRegToStackSlot for reg1 // do something // loadRegFromStackSlot for reg1 end ---- I tried looking in the LLVM

Each of the data sets contains monthly observations on price indices for 7 countries. I use the fitted values from reg1 in the reg2 model. The interior loop executes without error as long as I explicitly specify the data set, i.e. data=dat70. However the code fails to execute if I specify the model in the form of the commented line, i. e reg1 <-dynlm(form1,data=Dnames[j]) I get the following

Hi All, While reading LLVM source code, sometimes I am wondering when should we use auto instead of iterator/const_iterator. I want to use the patch [1] I sent before as an example. Could someone give me advice/guideline here? Also, I have another question. Sometimes the for-loop uses const_iterator, say for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();