Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] ifconversion following br_cc instructions"
2016 Mar 29
0
IfConversion and representation of predicates
Hello,
I have a few questions about applying the IfConversion pass to my out-of-tree target.
(1) Is it true that the IfConversion pass may only run after register allocation?
I often encounter this bad scenario, and I think it could be entirely avoided if IfConversion ran before register allocation: the block-to-be-predicated contains load-immediate (LI) instructions. The LI instructions
2014 Aug 01
2
[LLVMdev] BR_CC questions
I am implementing a new backend and am pretty sure I don't quite understand "the way" one is supposed to implement conditional branches.
My target CPU natively supports a conditional branch instruction that accepts a condition to test (equal, less than, etc.), two operands (two registers, or one register and one immediate), and finally a target PC to branch to if the comparison
2012 Oct 31
3
[LLVMdev] : Predication on SIMD architectures and LLVM
Hi all,
I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this
2012 Nov 01
0
[LLVMdev] : Predication on SIMD architectures and LLVM
On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote:
> Hi all,
>
> I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we
2009 Dec 11
1
[LLVMdev] combine ISD::SETCC by custom routine
hi Eli,
thanks for reply :)
i am currently decompose the BR_CC node to a target SETCC node and a
target BRCOND node, but since BR_CC node sometimes is combine from a
BRCOND node and SETCC node, so i just wondering if theres any better
way :)
regards
--ether
2010 Nov 24
1
[LLVMdev] Selecting BRCOND instead of BRCC
Hi everyone,
I have the following code (as part of a larger function):
%0 = icmp eq i16 %a, 0 ; <i1> [#uses=1]
br i1 %0, label %bb1, label %bb
I would like to match this with a BRCOND, but all I get is an error message
when compiling the above code that say:
LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00,
0x170dc60, 0x170ec00, 0x170ef00 [ID=19]
2017 Mar 07
2
Specifying conditional blocks for the back end
Hello.
Because I experience optimizations (DCE, OoO schedule) which mess the correct
semantics of the list of instructions lowered in ISelLowering from the VSELECT LLVM
instruction, and these bad transformations happen even before scheduling, at later I-sel
subpasses, I try to fix this problem by lowering VSELECT to only one pseudo-instruction
and LATER translate it to a list of
2016 Mar 15
2
how to type-legalize a dag
On Tue, Mar 15, 2016 at 2:21 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 3/15/2016 4:16 PM, Rail Shafigulin via llvm-dev wrote:
>
>> Below is the output of llc with a -debug-only=isel. As you could see the
>> output type for load, store, and add changes from v4i32 to i32 during
>> legalization. How can I preserve the output type to
2014 Jun 16
2
[LLVMdev] Machine level IfConversion for ARM
Hi All,
How can I run the IfConversion pass in JIT to optimize my code for ARM as a
Target Architecture?
--
View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513.html
Sent from the LLVM - Dev mailing list archive at Nabble.com.
2013 Feb 06
0
[LLVMdev] Incorrect Simple pattern matching in lib/CodeGen/IfConversion.cpp
Hello!
The if-converter tries to match 'Simple' patterns looking like this:
// Simple (split, no rejoin):
// EBB
// | \_
// | |
// | TBB---> exit
// |
// FBB
The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461)
checks if TBB matches this pattern. It basically does this by simply
checking if AnalyseBranch fails on
2013 Jul 01
0
[LLVMdev] IfConversion non-recursive patch.
Hi.
On our system we have a problems with recursive IfConversion algorithm.
Here is the patch for making it loop-based.
Or do I need to send it to some other mail-list?
--
Best regards, Andrew Zhogin.
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2014 Jul 14
2
[LLVMdev] Getting SELECT_CC and BR_CC DAG nodes
Hello,
I'd like to write some unit tests which verifies SELECT_CC and BR_CC
lowering for ARM target, but I'm almost completely unfamiliar with
llvm/Target. How can I get this nodes in DAG?
Thanks.
--
Kind regards, Dmitry Borisenkov
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2017 Oct 11
2
{ARM} IfConversion does not detect BX instruction as a branch
On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote:
>
> Hi all,
>
> I got a silly bug when compiling our project with the latest Clang. Here's
> the outputted assembly:
>
> tst r3, #255
> strbeq r6, [r7]
> ldreq r6, [r4, r6, lsl #2]
> strne r6, [r7, #4]
2014 Feb 12
2
[LLVMdev] ifconversion before register allocation
Hi all,
I am using llvm backend to generate binary for a specific accelerator. I
would like to convert instructions into predicated form when instructions
are still in SSA form. It looks like that ifconversion execution flow is
different when instructions are in SSA form. However, I am encountering
many problems (specially with registers) when I use it before register
allocation. I was wondering
2014 Jun 18
2
[LLVMdev] Machine level IfConversion for ARM
I need to do some analysis, in which I have to selectively convert IFs. I am
trying to find a way to call this optimization pass from the JIT code, thus
I can decide which branches to convert and which to keep. Apparently I
cannot do this using a pass manager.
--
View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513p69622.html
Sent from the
2020 Mar 24
3
Questions on ifconversion and predication
Assume an architecture that has multiple condition code registers, e.g., powerpc.
Now assume that there are predicate instructions like thumb2, but can specify
which condition code register they refer to.
Now also assume that these predicate instructions themselves are predicatible,
if executed they change the current predication state.
Can LLVM handle multiple levels of predication?
When is
2009 Dec 11
0
[LLVMdev] combine ISD::SETCC by custom routine
On Fri, Dec 11, 2009 at 1:49 AM, ether zhhb <etherzhhb at gmail.com> wrote:
> hi,
>
> i have a backend that want to do custom combine on SETCC nodes.
>
> but some time SETCC was combined into BR_CC before i can visit it to
> do my own combine, because DAGCombiner always do its own combine
> before custom combine. so, is there anyway to prevent it being
> combined
2017 Jan 10
2
[PATCHish] IfConversion; lost edges for some diamonds
On Tue, Jan 10, 2017 at 2:31 AM, Peter A Jonsson <pj at sics.se> wrote:
> Hi Kyle,
>
> my apologies for mailing you directly but it seems new user creation is
> disabled on the llvm bugzilla.
>
> We sometime lose edges during IfConversion of diamonds and it’s not
> obvious how to reproduce on an upstream target. The documentation for
> HasFallThrough says *may*
2007 Jun 14
1
[LLVMdev] Node definitions, Pseudo ops and lowering SELECT/COND_BRANCH to branch instructions
Hello,
Im back trying to finish my backend to a simple RISC cpu SABRE now
that most of the tedious process of examining undergraduate students
is out of the way. I have managed to describe the registers and the
instructions in the architecture and have added support for 32 bit
immediates (thanks to Christopher Lamb) as the instruction set only
supports 17 bit immediates directly.
Could
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
Hi all,
I got a silly bug when compiling our project with the latest Clang.
Here's the outputted assembly:
> tst r3, #255
> strbeq r6, [r7]
> ldreq r6, [r4, r6, lsl #2]
> strne r6, [r7, #4]
> ldr r6, [r4, r6, lsl #2]
> bx r6
For the code to execute correctly, either the _ldr_ should be a _ldrne_
instruction or the _ldreq_ instruction should be removed. The error
seems to