similar to: [LLVMdev] llvm-3.0rc2 build error on linux/ppc

Nello,it is known issue ;) You may work around to add -UPPC. http://llvm.org/bugs/show_bug.cgi?id=10969 FYI, LLVM RC2 passes on ppc-linux. http://bb.pgr.jp/builders/clang-ppc-linux/builds/125 ...Takumi

hi, i just try to build llvm-3.0 (stable) on linux ppc32 (CRUX PPC 2.7) with gcc-4.5.3, binutils-2.21.1, glibc-2.12.2 . As this suggestion: http://llvm.org/bugs/show_bug.cgi?id=10969 I applied a patch like this one: --- llvm-3.0.src/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h 2011-07-26 01:24:55.000000000 +0200 +++ llvm-3.0.src/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

On Fri, 2011-12-02 at 06:58 -0600, Hal Finkel wrote: > Nico, > > There is a third place that '#undef PPC' is needed (at the top of > PPCFixupKinds.h). Alternatively, you can run configure with -UPPC in > your CPPFLAGS. I'll try to get this fixed in trunk shortly. I just tested this, and I was wrong: passing -UPPC to configure in CPPFLAGS does not work for some reason.

Nico, There is a third place that '#undef PPC' is needed (at the top of PPCFixupKinds.h). Alternatively, you can run configure with -UPPC in your CPPFLAGS. I'll try to get this fixed in trunk shortly. -Hal On Fri, 2011-12-02 at 12:30 +0100, acrux_it at libero.it wrote: > hi, i just try to build llvm-3.0 (stable) on linux ppc32 (CRUX PPC 2.7) with > gcc-4.5.3, binutils-2.21.1,

I'm looking for a driver for and old uninterruptible power supply (UPS), Eaton Powerware 9125 2500U. I want to use it with my FreeNAS server. I looked a the list and didn't see a driver for it: http://www.networkupstools.org/stable-hcl.html?manufacturer=Eaton I see a driver for the 9130; any idea whether it will work with a 9125? Any other ideas for connecting the 9125 to a FreeNAS

On Sep 19, 2014, at 4:03 PM, Nello Lucchesi <nello at octobergroup.com> wrote: > I'm looking for a driver for and old uninterruptible power supply (UPS), Eaton Powerware 9125 2500U. I want to use it with my FreeNAS server. > > I looked a the list and didn't see a driver for it: > > http://www.networkupstools.org/stable-hcl.html?manufacturer=Eaton > > I see a

Hi, attached is a patch to improve including targets other than X86 in CMake MSVC builds. When adding libs to link, rather than always using LLVMX86CodeGen and LLVMX86AsmPrinter, it grabs the correct ones. It also adds "force-link-ints" to the various TargetMachine cpp files, as well as X86AsmPrinter and PPCAsmPrinter. These are needed to be able to encourage the Win32 linker to

Hi Gents, For those of us with out-of-tree backends which are not 32bit, the msp430 backend is a useful vehicle for examining changes and testing out ideas. So I was wondering about enabling debug output on the MSP430 backend so that I can illustrate a few issues to Adrian and you on the variable pieces side. (there doesn't appear to be any specific person claiming the msp430 code right

Attached is a working patch set for llvm to be able to emit arm64 (currently as triple aarch64-apple-ios) mach-o object files, in case someone is interested. I'm not sure if the llvm maintainers want the patch given the previous message that there's going to be an official patch set from apple to support this, but here is mine. What works (tested on an iPhone 5S): * objc strings,

Hi, I've run Clang Static Analyzer checker alpha.cplusplus.NewDeleteLeaks over LLVM codebase to detect false-positives and at the same time eliminate memory leaks. The majority of leaks were detected in lib/Target/* and lib/MC/*. In all cases the similar trick was detected as a leak (example from lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp) : static MCStreamer

As part of my ELLCC project (http://ellcc.org), I build clang/LLVM on my native x86_64 Linux box and then use it to compile itself. For further sanity checking, I then use that copy to cross compile for other targets (arm, armeb, i386, microblaze, mips, mipsel, ppc, and x86_64). After updating to a recent TOT revision, r195452, I get a strange error when cross compiling for the i386:

Good day Im working with some coordinates, and want to create a PPP object, I found that error: > Datos=read.table("puntos_texto.txt",dec=".",sep="\t",header=T) > summary(Datos) id y x Min. : 1.0 Min. :1013581 Min. :1177842 1st Qu.: 821.2 1st Qu.:1014442 1st Qu.:1179658 Median

Hi, I have an application, script.exe, written under mono framework and for execute them in my linux box I must write in console: mono script.exe The problem is that when I call this application in dialplan with command: exten => 500,1,System(mono script.exe) the application not run! Somebody can help me to find the problem? Thanks! -------------- next part -------------- An HTML

Hello, I run into a problem that llvm can't write the correct ELFHeaderEFlags for hexagonv4. The following patch can fix it. Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (revision 265917) +++

Hello all, I would appreciate your thoughts on a seemingly simple problem. I have a database, where each row represent a single record. I want to aggregate this database so I use the aggregate command : D<-read.csv("C:\\Users\\test.csv") attach(D) by1<-factor(Class) by2<-factor(X) W<-aggregate(x=Count,by=list(by1,by2),FUN="sum") The results I

My apologies. Shouldn't it just be removed since it is now in a subdirectory? On 12/15/2011 11:38 PM, Marc J. Driftmeyer wrote: > File: trunk/llvm/lib/Target/Hexagon/CMakeLists.txt > > set(LLVM_TARGET_DEFINITIONS Hexagon.td) > > tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) > tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) > tablegen(LLVM

Please include a testcase with the patch. gas uses " nopl 0x0(%eax)" for k6_2. Are you sure it is a gas bug? On 3 November 2013 13:50, Mikulas Patocka <mikulas at artax.karlin.mff.cuni.cz> wrote: > Hi > > This patch fixes code generation bug - 586-class CPUs don't support the > nopl instruction and some 686-class CPUs don't support it too. > > I

Hi This patch fixes code generation bug - 586-class CPUs don't support the nopl instruction and some 686-class CPUs don't support it too. I created bug 17792 for that. BTW. I think you should also optimize padding on these CPUs - instead of a stream of 0x90 nops, you should generate variants of "lea (%esi), %esi" instruction like gcc. This patch disables generation of

Hi, I'm from Intel compiler department. I am proposing the integration of a backend targeting Nios II processor architecture. Nios II is a 32-bit general-purpose RISC processor core designed specifically for the Altera family of FPGAs. All information at about Nios II can be found at Altera website https://www.altera.com/products/processors/support.html, including the current ISA

File: trunk/llvm/lib/Target/Hexagon/CMakeLists.txt set(LLVM_TARGET_DEFINITIONS Hexagon.td) tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel) tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv) tablegen(LLVM