similar to: [LLVMdev] gp/GOT

I'm getting this error in my mips16 port. I think that PHI replacement is done in some target independent phase. In the process of debugging this. Maybe to someone else it's obvious how this can happen . tia, Reed *** Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor! *** - function: main - basic block: BB#0 entry

On Tue, Jan 8, 2013 at 6:33 PM, reed kotler <rkotler at mips.com> wrote: > On 01/08/2013 01:48 PM, Eli Friedman wrote: >> >> On Mon, Jan 7, 2013 at 6:07 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> For example: >>> >>> /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel >>> -relocation-model=pic -o

On 01/08/2013 01:48 PM, Eli Friedman wrote: > On Mon, Jan 7, 2013 at 6:07 PM, reed kotler <rkotler at mips.com> wrote: >> For example: >> >> /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel >> -relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float > Try something like the following: > > float f; > double test(void*

For example: /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel -relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float On 01/04/2013 07:45 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler

Hi Bob, This has turned out to be what appears to be a very obscure binutils bug. I'm working on a test case for it now. I have a patch for Mips16 llvm which works around the issue for now. In general, pure risc architectures have no pity for compiler and toolchain developers. Mips16 is way more extreme in this way than mips32. In mips32, there is no PC register or PC relative

On Mon, Jan 7, 2013 at 6:07 PM, reed kotler <rkotler at mips.com> wrote: > > For example: > > /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel > -relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float Try something like the following: float f; double test(void* fptr) { f = ((float(*)(float,float))fptr)(1.0, 1.0); } -Eli

On Mon, Jan 7, 2013 at 4:16 PM, reed kotler <rkotler at mips.com> wrote: > On 01/04/2013 07:45 PM, Eli Friedman wrote: >> >> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>>> >>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com>

I definitely trust what you say now with time to think at your keyboard over what you said on the spot in a live presentation. The comment that I was referring to was: 36:44 of http://llvm.org/devmtg/2012-04-12/videos/Reed_Kotler-mobile.mov "there's not really more than a couple thousand lines of .td ... I mean there's not tons of this code so if we had to use a different one I

On 12/15/2012 12:53 PM, Chandler Carruth wrote: > On Sat, Dec 15, 2012 at 12:33 PM, Reed Kotler <rkotler at mips.com > <mailto:rkotler at mips.com>> wrote: > > I have an approved target independent putback and i've run all > that we have at Mips as well as on x86 " make TEST=simple" > > Is there anything else that is easy to run that I

Hi Sean, Glad to hear there is clean up of tablegen going on. Just for the record, I don't know what you are referring to regarding some comment of mine at my talk about 10K LOC. I don't know how big tablegen is itself nor how much code has been written in it so I would not have ventured such a guess. The idea of totally replacing the tablegen language came up at the talk during the

On 02/24/2014 04:42 PM, Eric Christopher wrote: > On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at mips.com> wrote: >> I need to leave soon and will take a look in the morning. >> >> I did look at the autoconf input files configure.ac >> >> There is a disable-zlib but not a disable-valgrind, even though it seems >> like there used to be.

> For those doing new ports, you might be interested to study how I did the td > files for mips16. There is still some cleanup I will do but essentially I > have cleanly layered the abstraction into four layers: > 1) machine formats > 2) assembly syntax > 3) instructions (none with patterns) > 4) patterns. Maybe you could write a bit more in-depth about this?

Turned out to be a rather simple fix. Just copied SP to a virtual register in the beginning of the function. Then added an extra operand to the DAGs with stack reference load/store, with the extra operand equal to this virtual register if the Parent of the address is a LOAD/STORE of an 8 or 16 bit quantity. It worked fine. When needed SP got copied to a mips 16 register and when the SP alias

On 01/04/2013 07:45 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >>>> I'm working on mips16 hard float which at a first approximation is just >>>> soft

I used the A9 schedule as an example: http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td The documentation could use more clarity, but this is how I was able to do it to always get two specific instructions to be scheduled together. ________________________________________ From: reed kotler [rkotler at mips.com] Sent: Tuesday, September 17, 2013 8:54 PM To: Micah Villmow

I need to leave soon and will take a look in the morning. I did look at the autoconf input files configure.ac There is a disable-zlib but not a disable-valgrind, even though it seems like there used to be. You can find scripts on the internet when you google of people adding disable-valgrind to configure. I can probably implement disable-valgrind in configure.ac. Reed On 02/24/2014 04:33

That doesn't actually give you a guarantee that they won't be split up. Phases other than the scheduler may insert instructions in the middle of block (constant island pass, for example). Pseudo-instructions are the canonical answer to that problem. --Owen On Sep 17, 2013, at 11:09 PM, Micah Villmow <micah.villmow at smachines.com> wrote: > I used the A9 schedule as an

On 03/10/2014 03:37 PM, Eric Christopher wrote: > cc'ing Bill as Release Manager > > On Mon, Mar 10, 2014 at 2:53 PM, reed kotler <rkotler at mips.com> wrote: >> I'm trying to understand how Mips will fit into the official release >> procedure. >> >> There are two Mips compilers: >> 1) The X86 resident llvm/clang compiler that can generate

I see what my problem is here.... I'll continue to move further. Seems like Richards fix is still okay. On 02/25/2014 02:42 PM, Eric Christopher wrote: > On Tue, Feb 25, 2014 at 2:41 PM, reed kotler <rkotler at mips.com> wrote: >> On 02/25/2014 02:38 PM, Eric Christopher wrote: >>> On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote:

On 09/17/2013 04:51 PM, Micah Villmow wrote: > Reed, > Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case. > > Micah > I'm not sure exactly what you mean. Can you point me to an example of that? TIA. Reed >>