similar to: [LLVMdev] Itineraries in the powerpc backend

Thanks Hal. On Fri, Oct 28, 2011 at 2:19 AM, Hal Finkel <hfinkel at anl.gov> wrote: > Carter, > > In my opinion (and I was the one who committed the changes in question), > it depends on the hardware. The pipeline descriptions are for the PPC > 440, which is an embedded PPC chip use in a variety of places. As such, > it is a fairly specific target, and using

Carter, In my opinion (and I was the one who committed the changes in question), it depends on the hardware. The pipeline descriptions are for the PPC 440, which is an embedded PPC chip use in a variety of places. As such, it is a fairly specific target, and using pipeline-hazard-based scheduling for specific embedded targets is not uncommon. The backends for ARM and MBlaze have similar pipeline

I hope you don't mind if do have a follow up question- is code in place in the code generation supporting "proper" scheduling via the processor itineraries in LLVM? On Fri, Oct 28, 2011 at 8:47 PM, Carter Cheng <cartercheng at gmail.com> wrote: > Thanks Hal. > > On Fri, Oct 28, 2011 at 2:19 AM, Hal Finkel <hfinkel at anl.gov> wrote: > >> Carter,

Hi everyone I'm fairly new with LLVM and I've been searching around but couldn't find info on this subject. I started working on a target for a new cpu and I realizing my initial simple understanding of instruction itineraries may be completely off. I'm trying to model a CPU that has a latency of 2 cycles for multiplications fully pipelined (so it can start a new one after one

On Mon, Aug 15, 2011 at 4:03 PM, Miguel G <miguel at esenciatech.com> wrote: > Hi everyone > I'm fairly new with LLVM and I've been searching around but couldn't find > info on this subject. > I started working on a target for a new cpu and I realizing my initial > simple understanding of instruction itineraries may be completely off. > I'm trying to model a

Hello, Is there code in place for lowering the bitcode SSA into an optimized sequence for the itineraries? I have been curious whether or not such descriptions exist for the x86 family or whether there are techniques to make a clear determination of this information. Regards, Carter. -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Nov 1, 2011, at 1:03 AM, Carter Cheng wrote: > Is there code in place for lowering the bitcode SSA into an optimized sequence for the itineraries? I have been curious whether or not such descriptions exist for the x86 family or whether there are techniques to make a clear determination of this information. This thread might partially answer your question:

Thanks Eli. Somehow I was assuming the scheduler would insert NOPs to enforce latencies The CPU I'm dealing with doesn't automatically stall, i.e. latency must be ensured by the program. As an alternative to a pass, is it feasible to modify the scheduler to do so (optionally) or it would be too complicated. If possible, what would be the right place to look ? Thanks so much Miguel On

I'm trying to build a standalone assembler for Mips using AsmParser. Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. I am getting an assertion for what I believe are multiple register definitions with the same name. llvm-tblgen:

On Jan 31, 2012, at 1:26 PM, Carter, Jack wrote: > I'm trying to build a standalone assembler for Mips using AsmParser. > > Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. > > I am getting an assertion for what I believe are

Hi Jack, You're running into a fundamental problem with the current table generated asmmatcher. Specifically, wants to believe that assembly parsing is context insensitive, or at least close enough that operands can be parsed w/o knowing the context of the instruction. Its idea is to use the operand types to disambiguate which instruction should be selected. It sounds like MIPS 64vs.32 does

Hello, I was looking over the documentation support for exceptions and it indicates that the invoke unwind support is incomplete. Is this still the case in 2.9? Regards, Carter. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110814/400bcca0/attachment.html>

Is there a way to convert between SchedMachineModel and Itineraries? I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would

I have been working on a LLVM backend for the MicroBlaze soft-processor: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze Attached is the initial MicroBlaze patch. It does the following: 1. Adds mblaze as a target in configure and configure.ac 2. Adds mblaze specific intrinsics in include/llvm/IntrinsicsMBlaze.td and include/llvm/Intrinsics.td 3. Adds mblaze

I have been working on getting ELF object file writing working for the MBlaze backend. Currently, each supported backend calls ELFObjectWriter::createELFObjectWriter from within the backend's TargetAsmBackend::createObjectWriter method. The createELFObjectWriter method then creates a new backend specific ELFObjectWriter class (either X86ELFObjectWriter or ARMELFObjectWriter) by decoding a

All, I am working on a scheduler for X86 and would like to include instruction latencies. It appears that this information is gathered from instruction itineraries, but that there isn't an itinerary for X86. I also can't seem to find documentation on how to add this for X86. Any pointers would be helpfull. Aran -------------- next part -------------- A non-text attachment was

Is there a way to express a multiple pipeline itinerary using the current scheme (maybe some trick with setting NextCycles = 0)? Specifically, consider a case where a floating-point load simultaneously uses units from a floating-point pipeline and a load/store pipeline. Thanks in advance, Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory

conmfigure does not accept mblaze nor mblaze-elf as target. checking target system type... Invalid configuration `mblaze': machine `mblaze' not recognized configure: error: /bin/bash ../../spare/llvm/autoconf/config.sub mblaze failed However with microblaze it proceeds fine. But when i try to use clang i get: clang: error: 'microblaze-unknown-none': unable to pass LLVM bit-code

The MBlaze backend seems to be essentially unmaintained since 2011. The maintainer (Wesley Peck who is BCC'ed) seems to have vanished, and in fact all emails to him are bouncing. I propose to remove the MBlaze backend on Friday if none step forward as a maintainer. Currently, folks are having to keep it up to date when changing shared parts of the backend with no help. -Chandler

It it possible to specify an instruction latency in the itinerary through a command line option? We have several options for a hardware divider which have different latencies and it would be nice if I could specify it through a compiler option rather than changing the value in the code and recompiling llvm every time? Any help is appreciated. -- Rail Shafigulin Software Engineer Esencia