Displaying 9 results from an estimated 9 matches similar to: "[LLVMdev] Emulate i64 add with 3 instructions"
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Bill,
Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
define other classes, but with using patterns inside of a multiclass to
reduce redundant code.
For example:
multiclass IntSubtract<SDNode node>
{
def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
def _i32 : Pat<(sub
2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Tue, Feb 10, 2009 at 8:27 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Bill,
> Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
> define other classes, but with using patterns inside of a multiclass to
> reduce redundant code.
> For example:
> multiclass IntSubtract<SDNode node>
> {
> def _i8 : Pat<(sub
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace =
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Is there a way to define a multi-class pattern in tablegen?
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
S1-609 One AMD Place
Sunnyvale, CA. 94085
P: 408-749-3966
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2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Is there a way to define a multi-class pattern in tablegen?
>
Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td, et al.
-bw
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
I'm not at the machine that has the changes, but it was failing at index 0.
Micah
From: Owen Anderson [mailto:resistor at mac.com]
Sent: Thursday, April 19, 2012 3:35 PM
To: Villmow, Micah
Cc: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output
2006 Jul 07
0
[patch] s390: fix six parameter handling in sysstub.ph
From: Peter Oberparleiter <peter.oberparleiter at de.ibm.com>,
Heiko Carstens <heiko.carstens at de.ibm.com>
Change s390's sysstub.ph so it can also handle syscalls with six parameters.
Signed-off-by: Peter Oberparleiter <peter.oberparleiter at de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens at de.ibm.com>
---
usr/klibc/arch/s390/sysstub.ph | 73
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your and-with-immediate?
-Owen
On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> I am trying to make
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version.