similar to: [LLVMdev] Adding fixups and relocations late in code generation

On Oct 10, 2011, at 10:11 AM, Jack Carter wrote: > Gang, > > I'm tasked with direct object generation for Mips and am trying to not > hack the code. > > I how exactly does one set an expression to be PC relative and if the > compiler can resolve it, not produce a relocation? > Fixups are created for all expressions that may need a relocation. The MC layer evaluates

Jim, Both the branch and the branch target are in the same function. This is known delta and should not matter where it is relocated because the delta will remain the same once it is a .o or later. I just want to know how to tell the compiler that this expression is target offset - branch offset. More generally, I want to know the rules for setting up expressions in general. I have no idea if

Hello, I notice that the program compiled by llvm-trunk compiler can't run correctly on hexagon-sim. The problem may caused by unimplemented backend applyFixup function. void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/, unsigned /*DataSize*/, uint64_t /*Value*/, bool /*IsPCRel*/) const override { return; } Best regards, Mingjie

Big thanks, i've managed to find what's going on. The thing that dumbfolded me a couple of times was that the error was thrown in one of the MCAssembler methods, but never in applyFixup() itself. On Thu, Jan 19, 2017 at 8:46 PM, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 1/19/2017 10:21 AM, Peter Bel wrote: > >> Hi, >> >> For the function call -

Hi everyone. In ARMAsmBackend.cpp, in routine DarwinARMAsmBackend::ApplyFixup() there is a curious call to getFixupKindNumBytes() - which can return 1,2, 3, or 4 depending upon the FixupKind The code in ApplyFixup() seems to be lifted from the X86. AFAIK, the initial Fixup.Offset() is always divisible by 4, at least for ARM mode - i.e. it is always at the instruction boundary. it looks like

Hi, I have added Branch condition BGEID like below… *def : Pat<(brcond (setcc (i32 GR32:$L), (i32 GR32:$R), SETGE), bb:$T),* * (BGEID (CMP GR32:$L, GR32:$R), bb:$T)>;* *def BGEID : TBT<0b101110, (outs), (ins GR32:$ra, brtarget:$offset), "bgeid\t$ra,$offset", [], IIC_BRc> {* * let rd = 0b10101;* *}* *def brtarget : Operand<OtherVT>* *{*

Hi llvm-dev, Our code base has a ancient copy of llvm (ver 3.5.1), and it uses the LLVM code gen for some domain-specific language. The previous dev left a global lock around the usage of LLVM code gen stating that because LLVM code gen can only be accessed single-threaded it needs to be protected with this global lock. But now this lock has caused some perf issues as we pretty much lose

Thank you Johannes, I looked it up and it seems that we're creating one LLVMContext per compilation "unit", not sure if that matters. i.e. there's no single globally shared LLVMContext object. Is LLVMContext *the* concurrency isolation (or unit) here? On Wed, Apr 3, 2019 at 6:34 PM Doerfert, Johannes <jdoerfert at anl.gov> wrote: > Do you use one llvm context or one

Hi, For the function call - yes, probably. But what about branching inside one function (standard if-then for example)? For example: echo "int g() { int a = 1; if (a > 3) return 1; return 0; }" | clang -x c - -o /tmp/a.o -c && objdump -d /tmp/a.o Thanks, Petr On Thu, Jan 19, 2017 at 8:06 PM, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 1/19/2017 9:11

Hi Jim, The diff below is not intended to be a patch, but a starting point. It is the shortest path (I hope) to getting LLVM to emit ARM mapping symbols to the ELF without changing any shared interfaces. Could you have a look at the FIXME comments and offer some pointers on how to get this code out of MCELFStreamer? Thanks, Greg diff --git a/lib/MC/MCELFStreamer.cpp b/lib/MC/MCELFStreamer.cpp

When I compile this LLVM IR…. @0 = private constant [19 x i8] c"V4main10Brightness\00", section "__TEXT,__swift3_typeref, regular, no_dead_strip" @1 = private constant [9 x i8] c"Vs5UInt8\00", section "__TEXT,__swift3_typeref, regular, no_dead_strip" @2 = private constant [18 x i8] c"currentBrightness\00", section "__TEXT,__swift3_reflstr,

Attached is an example of how to reproduce the issue. It uses a C file that happens to has a bunch of switch statements which are encoded as jump tables, giving us data-in-code. Usage: To build object files with clang via the -integrated-as versus via GCC: $ export NDK_DIR=<my_ndk_dir> $ export LLVM_DIR=<my_llvm_bin_dir> $ make To test that the generated objects contain the same

Attached is a working patch set for llvm to be able to emit arm64 (currently as triple aarch64-apple-ios) mach-o object files, in case someone is interested. I'm not sure if the llvm maintainers want the patch given the previous message that there's going to be an official patch set from apple to support this, but here is mine. What works (tested on an iPhone 5S): * objc strings,

This attempts to address http://llvm.org/bugs/show_bug.cgi?id=18220 It also fixes a test which was requiring the *wrong* output. I'm relatively happy with this part, and it even solves most of the hard part of feature request for .code16 in bug 8684 — which was actually why I started prodding at this. But I could do with some help with the 16-bit signed relocation handling, which I've

Sorry, forgot to Reply-All. Begin forwarded message: > From: Steve Montgomery <stephen.montgomery3 at btinternet.com> > Subject: Re: [LLVMdev] Prevention register promotion at the isel codegen phase > Date: 24 November 2012 17:09:58 GMT > To: Joseph Pusdesris <joe at pusdesris.com> > > I had a similar problem trying to implement reg-mem operations. The solution I

Yes, this is very helpful! Thank you! How does this work when exiting a variable's liveness range? Will it automatically know to free the stack slot for reuse? -Joe On Sat, Nov 24, 2012 at 12:23 PM, Steve Montgomery < stephen.montgomery3 at btinternet.com> wrote: > Sorry, forgot to Reply-All. > > Begin forwarded message: > > *From: *Steve Montgomery

On 06/22/2010 11:11 AM, Patrick Marlier wrote: > On 06/21/2010 08:21 PM, Eric Christopher wrote: >> On Jun 21, 2010, at 2:56 AM, Patrick Marlier wrote: >> >> >>> Hello, >>> >>> This bug affects all LLVM versions from 2.6 to trunk : >>> http://llvm.org/bugs/show_bug.cgi?id=5081 >>> >>> The workaround I found is to

On Wed, 2018-02-07 at 21:55 +0000, David Woodhouse via llvm-dev wrote: > Can you take care of filing the tickets for %V0 and "=q" > and attribute__((indirect_branch("keep"))) please? With those fixed, I > think we should be OK again. Here's %V0 support, which makes the hypervisor guest support build. diff --git a/lib/Target/X86/X86AsmPrinter.cpp

On 06/21/2010 08:21 PM, Eric Christopher wrote: > On Jun 21, 2010, at 2:56 AM, Patrick Marlier wrote: > > >> Hello, >> >> This bug affects all LLVM versions from 2.6 to trunk : >> http://llvm.org/bugs/show_bug.cgi?id=5081 >> >> The workaround I found is to add this : >> >> Index: lib/Target/X86/X86Instr64bit.td >>

On Jul 7, 2010, at 4:52 AM, Patrick Marlier wrote: > Which one is correct ? > - movl $tm_nest_level at TPOFF, %ecx > or > - movq $tm_nest_level at TPOFF, %rcx > or > - movl tm_nest_level at TPOFF, %ecx > I believe this is initial exec and so from: http://people.redhat.com/drepper/tls.pdf it would be movl tm_nest_level at TPOFF, %ecx > Otherwise, Is there a