similar to: [LLVMdev] VirtRegRewriter.cpp: LocalRewriter::ProcessUses()

On Oct 7, 2011, at 8:14 AM, Jonas Paulsson wrote: > Hi, > > I think I've found a bug in this method. > > I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. > > For the def-operand, with a subregindex, an implicit-use operand was added with this code: > >

Yes, I'm saying that the implicit-def operand that was added in this case ended up as #4, out of 6, when the operands list was reallocated in addOperand(). If addOperand was rewritten, I think it's best not to add my fix for ProcessUses(), as I wrote earlier. Jonas Subject: Re: [LLVMdev] VirtRegRewriter.cpp: LocalRewriter::ProcessUses() From: stoklund at 2pi.dk Date: Wed, 12 Oct 2011

llvm-dev, Thanks so much in advance for any help, tips, or advice you may be able to offer me. I'm going to try to avoid the big-picture description of the project I'm working on, and only talk about the parts that I have trouble with / currently need to implement. -- I've been starting by taking the source code from the "llvm-mc" tool, and working that down into a

Is it possible to get a virtual register and then use that to create a real register? I've seen it done in unittests/CodeGen/MachineInstrTest.cpp like this: unsigned VirtualDef1 = -42; VD1VU->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); But when I do that in my code I get an assertion so I wasn't sure if it's legal or not. Thanks.

Jim/Tim/Renato, A few days ago (has it been weeks now?) we discussed a codegen problem on armv4t having to do with lo->lo register copies. I'd like to start that discussion again, this time with a patch. A brief summary of the problem for folks who didn't catch the discussion earlier, and those like me who forget what they ate for breakfast: ;] The mov instruction on armv4t

Hi all, There are many assertions sprinkled throughout the llvm codebase, which is a GoodThing. Most of the assertions even have informative messages, which is a BetterThing. However, assertion messages are static strings, and don't include any information about the particular object/value which caused the assertion. In a 'data oriented' system like llvm, this makes it really

I have a MachineOperand that could be something other than a Reg: mem, global address, imm, etc... I want to replace a reg MachineOperand with this non-reg MachineOperand. I've tried a few different things, but it doesn't seem like there is some simple functionality to do this? "RemoveOperand" and "addOperand" does not work. There doesn't seem to be a valid

Fernando, The code there should be more or less functional, though it's not currently used by anything. Eventually it should probably be moved to a method on MachineBasicBlock. The API breakage you're seeing is because some methods moved around. Feel free to fix it. :-) --Owen On Jan 26, 2008, at 6:31 PM, Fernando Magno Quintao Pereira wrote: > > Hi LLVMers, > >

Hi LLVMers, what is the status of breaking critical edges in machine functions? I just compiled the top of the LLVM tree, and I found llvm/CodeGen/BreakCriticalMachineEdge.h. But this file seems not to be up-to-date with the other classes in the top of the tree. For instance, it calls isTerminatorInstr on llvm::TargetInstrInfo, but this method is no longer there. If I want to break

Do your 32768 registers also have sub registers? I can't tell you exactly what to change. I'm not familiar with the code. I would just be running grep or something. ~Craig On Fri, Jul 14, 2017 at 10:23 AM, hameeza ahmed <hahmed2305 at gmail.com> wrote: > Thank you so much. I think there is no issue with my definitions since i > have to use larger registers i.e 65536 bit

I have made changes in 3 files: LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached here. Now i am getting following errors. which means registerinfo.inc file is not generated successfully. /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: no member named 'XMM8' in namespace 'llvm::X86' if ((RegNo >= X86::XMM8 && RegNo <=

Does anyone know exactly what ComposerIndices in Target.td is all about? I see just one place where it's used in X86 but it's not clear from the comments in Target.td and it's one usage, exactly what this feature is about. Tia. Reed

Hello, I've compiled today's LLVM on ARM/Linux machine and attempted to use our GHC/ARM port (which is using LLVM as a backend for generating machine code) with it but I've failed in compiling GHC alone as LLVM fails on me with following message: llc: /export/home/karel/vcs/llvm-ghc-arm/lib/CodeGen/MachineInstr.cpp:612: void llvm::MachineInstr::addOperand(const

Hello, Duncan. > 3-fortran.diff > Get fortran to compile: use the common stubs and rip out > the incomplete collection of dummy routines someone already put in. > With this patch, the fortran build dies at this point: > > cc1: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:367: void llvm::ScheduleDAG::AddOperand(llvm: > :MachineInstr*, llvm::SDOperand, unsigned int, const

On Mar 12, 2009, at 1:47 AM, someguy wrote: > However, assertion messages are static strings, and don't include any > information about the particular object/value which caused the > assertion. In a 'data oriented' system like llvm, this makes it really > difficult to pinpoint which node is actually triggering the assertion. > > For example, in

Hi, I'm new to LLVM. I'd like to know if there is a method I can call whenever I need any available CPU register. Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20181222/e916b214/attachment.html>

On Feb 20, 2013, at 1:27 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Feb 20, 2013, at 1:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> >> On Feb 20, 2013, at 11:44 AM, Jim Grosbach <grosbach at apple.com> wrote: >> >>> I'm not sure. It certainly seems reasonable to me that the building could/should set default

Hi Karel, Mind trying again with current top of tree? Owen's fixed a few things today that were manifesting with that error. -Jim On Aug 29, 2011, at 2:33 PM, Karel Gardas wrote: > Hello, > > I've compiled today's LLVM on ARM/Linux machine and attempted to use our GHC/ARM port (which is using LLVM as a backend for generating machine code) with it but I've failed in

Yes, the arch is just as you said, something like AMD GPU, but Intel GPU don't have separate register file for 'scalar/vector'. In fact my idea of defining the register tuples was borrowed from SIRegisterInfo.td in AMD GPU. But seems that AMD GPU mainly support i32/i64 register type, while Intel GPU also support byte/short register type. So I have to start defining the registers from