similar to: [LLVMdev] MIPS 32bit code generation

Hi, I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > Do you want to replace > > lui $2, %hi(g1) > addiu $2, $2, %lo(g1) > > with this? > la $2, g1 > > If that

I reiterate. You should fix the simulator. It is broken. The compiler is not. Fix what's broken. -Jim On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote: > Hi, > > I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, > > > > On Thu, Oct 6, 2011 at

Do you want to replace lui $2, %hi(g1) addiu $2, $2, %lo(g1) with this? la $2, g1 If that is the case, you can add this pattern. def op_la : Operand<i32>; def LA : FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), "la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>;

I don't think I ever said that the MIPS target is broken. I am simply trying to branch out one additional llc target for SimpleScalar PISA architecture. On Fri, Oct 7, 2011 at 2:41 PM, Jim Grosbach <grosbach at apple.com> wrote: > I reiterate. You should fix the simulator. It is broken. The compiler is > not. Fix what's broken. > > -Jim > > On Oct 7, 2011, at 1:11

Hi, for our micro-architecture research, we are using simplescalar 3.0 32bit mips simulator, which comes with binutils 1.5.2, and the ld fails at "lui" (bfd error). However, the ld is happy with "la" (assembler macro) and simulator correctly simulates. On Wed, Oct 5, 2011 at 5:04 PM, Eric Christopher <echristo at apple.com> wrote: > > On Oct 5, 2011, at 4:01 PM,

On Oct 5, 2011, at 4:01 PM, Gang-Ryung Uh wrote: > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Why? -eric

We are trying to use LLVM (Clang as the C frontend) to generate code for 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 sslittle-na-sstrix platform. Can you advise what would be the right way to use the LLVM compiler infrastructure? The following is the one I used, but it appears that it produce the code in big-endian (and I wonder whether the calling convention is right.) To

It will produce little-endian code if you replace "mips" with "mipsel". 1. clang -ccc-host-triple mipsel-unknown-linux -ccc-clang-archs mipsel -O3 -S -emit-llvm foo.c -o foo.ll 2. llc -march=mipsel -mcpu=4ke foo.ll -o foo.s (the -march option is redundant) If you do not specify the target cpu with -mcpu, by default it will generate code for Mips1, which has not been tested as

Hi, We have tried and generate assembly code for very simple test C code. But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code with the following complaints. Could you advise which version of bitutils that we need to use for mips code with LLVM with Clang? Thanks, $ GCC addr01.s addr01.s: Assembler messages: addr01.s:1: Error: Unknown pseudo-op: `.section'

Hi, I wonder what PRE algorithm is used for the GVN.cpp in LLVM. Any reference will be appreciated. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140930/3d7f74e3/attachment.html>

On Jul 15, 2011, at 10:13 AM, Gang-Ryung Uh wrote: > Hi, > > We have tried and generate assembly code for very simple test C code. But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code with the following complaints. Could you advise which version of bitutils that we need to use for mips code with LLVM with Clang? Thanks, Something released in the last 10

Hi, We would like to assemble .s file using binutils-2.5.2 which comes with simple-scalar3.0. Unfortunately, this particular version of binutils doesn't seem to handle global-offset-table (position independent code) and the some of the mips instructions. Thanks, On Fri, Jul 15, 2011 at 11:39 AM, Eric Christopher <echristo at apple.com>wrote: > > On Jul 15, 2011, at 10:13

We are using simplescalar 3.0 as an architecture simulation platform for our research. The current version of the simplescalar still uses gnu binutils 1.5. and gcc-2.7.2 to generate 32bit mips code. We are currently trying to replace gcc-2.7.2 by LLVM current. However, the generated code cannot be processed by this old binutils-1.5. We expect that it can be quite difficult to make simplescalar use

Hi, Target architecture for llc can be specified using -march, -mcpu, -mattr options. Is it possible to override target CPU attributes when using llvm-gcc compiler? Regards, Sergey Y.

Is it possible to configure llc to generate code for other architectures? For instance, what I need to do to generate Sparc machine code? Thanks. --Gang -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100316/253bd016/attachment.html>

A simulator should be expecting the machine opcodes not macros. LD shouldn't care at all as long as the object format plays well. I would think it would be better to fix the simulator. Jack ________________________________________ From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of llvmdev-request at cs.uiuc.edu [llvmdev-request at cs.uiuc.edu] Sent: Thursday,

I am having trouble trying to enable post RA scheduler for the Mips backend. This is the bit code of the function I am compiling: (gdb) p MF.Fn->dump() define void @PointToHPoint(%struct.HPointStruct* noalias sret %agg.result, %struct.ObjPointStruct* byval %P) nounwind { entry: %res = alloca %struct.HPointStruct, align 8 %x2 = bitcast %struct.ObjPointStruct* %P to double* %0 = load

Hi Johnny, Thank you for your help. I guess the pseudo instruction does not interfere in the generated assembly code. I'll check the file that describes the registers and I hope understand why the assembly code is printed wrong (now is printed things like add r1, r0, -40). Cheers, Carlos Carlos Almeida Jr On Thu, Nov 27, 2014 at 7:56 AM, Johnny Val <johnnydval at gmail.com> wrote:

I filed a bug report (Bug 12205). Please take a look when you have time. Per your suggestion, I also attached a patch which attaches to load or store nodes a machinepointerinfo that points to a stack frame object when it can infer they are actually reading from or writing to the stack. The test that was failing passes if I apply this patch, but I doubt this is the right approach, because this

On Mar 6, 2012, at 5:05 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > I am having trouble trying to enable post RA scheduler for the Mips backend. > > This is the bit code of the function I am compiling: > > (gdb) p MF.Fn->dump() > > define void @PointToHPoint(%struct.HPointStruct* noalias sret > %agg.result, %struct.ObjPointStruct* byval %P) nounwind {