similar to: [LLVMdev] Compiling LLVM w/ Clang for ARMv7 and ARMv6 archs from a i386 OSX machine

On Sep 22, 2011, at 11:47 AM, Valentin Radu wrote: > checking for armv7-apple-darwin-clang... no > checking for armv7-apple-darwin-llvm-gcc... no > checking for armv7-apple-darwin-gcc... no It's because you don't have a compiler around that targets arm by default. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Sep 22, 2011, at 11:51 AM, Eric Christopher wrote: > > On Sep 22, 2011, at 11:47 AM, Valentin Radu wrote: > >> checking for armv7-apple-darwin-clang... no >> checking for armv7-apple-darwin-llvm-gcc... no >> checking for armv7-apple-darwin-gcc... no > > It's because you don't have a compiler around that targets arm by default. Exactly right. You

Hi, I'm trying to compile llvm/clang so that: it is compiled on osx 10.6, it runs on osx, but it outputs win32 objects. More exactly, I'm building an app which generates a .c file that doesn't include or link with anything, and I'd like to be able to make a win32 .dll of it on osx. Below is what I'm getting. Full log is here: http://pastebin.com/KsPGvAfW It fails while

On Thu, 8 Jan 2015, Jonathan Lennox wrote: > Every armv7 (and armv8) iOS device has supported Neon, and Xcode support for > armv6 was dropped with Xcode 4.5. > > Even if you?re compiling with an old Xcode version to support really old iOS > devices, Apple?s armv6/armv7 selection was a compile-time switch (supported > using fat binaries). ?I think the arch can be detected based

Hi, I'm building LLVM on Mac OS 10.10 and I'm having trouble making LTO work. The system linker dumps the following information when I executed "ld -v" @(#)PROGRAM:ld PROJECT:ld64-241.9 configured to support archs: armv6 armv7 armv7s arm64 i386 x86_64 x86_64h armv6m armv7m armv7em LTO support using: LLVM version 3.4.2 which tells me that it is correctly pointing to the LLVM

Hi guys, I have this ODROID XU (quad-core ARMv7 Cortex A15 1,6 GHz) box that I want to make available to the LLVM project. I can see that LLVM already has an ARMv7 Cortex A9 system doing Clang, but how should this box be used, if at all? We're talking a long-term commitment within the realm of being a buildbot slave. It builds LLVM in about 40 minutes, excluding the test suite.

On Wed, Nov 13, 2013 at 4:53 PM, Mikael Lyngvig <mikael at lyngvig.org> wrote: > Hi guys, > > I have this ODROID XU (quad-core ARMv7 Cortex A15 1,6 GHz) box that I want > to make available to the LLVM project. I can see that LLVM already has an > ARMv7 Cortex A9 system doing Clang, but how should this box be used, if at > all? We're talking a long-term commitment

Hi everyone, I'm working on some custom transformation passes that have the side-effect of significantly increasing the code size. While testing it on some larger, real-world code bases, I run into a linker error for armv7 thumb code. The particular error I get from ld64 is that "armv7 has no pc-rel bx thumb instruction." I've been able to reproduce the problem by taking a

Hi, I think I discovered a major armv7 optimization bug in Clang. I create a simple test case which exhibits the issue. When you compile the attached file for armv7 with optimizations turned on (O2, O3 or Os), the binary generated led to a crash. The issue can't be reproduced when using GCC 4.2. It can't be reproduced with Clang when the optimization is turned off (O0). This issue can be

On Jan 12, 2015, at 2:45 PM, Rafael Espíndola <rafael.espindola at gmail.com> wrote: > On 10 January 2015 at 17:43, Rahman Lavaee <r.lavaee at gmail.com> wrote: >> Hi, >> I'm building LLVM on Mac OS 10.10 and I'm having trouble making LTO work. >> The system linker dumps the following information when I executed "ld -v" >> >>

> By the way, we are looking for ARM testers. There was a lot of interest in the 3.0 release for an ARM release. We will try to do one this release on a trial basis. We are looking for ARMv7 cortex-a8 and cortex-a9 on Linux. We have two pandard board (ARMv7 cortex-a9) and perhaps one ARMv6 4-cores board. Do we do a native compile or cross compile for the ARM platform? Regards, chenwj --

The problem is in your code, not the compiler. You're casting an unaligned char* to an int*, even though an int* pointer must be 4-byte aligned in every ARM ABI that I've ever seen. On Jan 23, 2012, at 6:14 AM, Alexandre Colucci wrote: > Hi, > > I think I discovered a major armv7 optimization bug in Clang. I create a simple test case which exhibits the issue. > When you

Guys, Could you please clarify if SMP available for XEN on ARMv7 with virtualizations extensions? Browsing through stuff for Arndale I do see enabling secondary CPU on XEN site and SMP enabling on dom0 kernel site. But I do not see SMP infrastructure implementation on the XEN site. Sincerely, Andrii Anisov. _______________________________________________ Xen-devel mailing list

Thanks Bradley. I see that the features set in /ARM.td/ get written to the generated file /<build>/llvm/lib/Target/ARM/ARMGenSubtargetInfo.inc./ Here the ProcA9 features appear in /ARMFeatureKV/ table: /{ "a9", "Cortex-A9 ARM processors", { ARM::ProcA9 }, { *ARM::FeatureFP16* } }, /With your change, the features for ProcA9 in the above entry are empty.//This

IMPORTANT! IMPORTANT! IMPORTANT! We will be branching for the 3.1 release on April 16th! :-) This gives us a little over two weeks to get the trees into the most stable condition we can. What this means for you: All major features for the 3.1 release should be finished or near completion by the April 16th. After April 16th, we will accept only bug fixes and patches which do not change the

Hi, Testing llvm trunk on openSUSE 13.1 ARMv7 I got 4 unexpected passes: Unexpected Passing Tests (4): LLVM :: ExecutionEngine/MCJIT/cross-module-sm-pic-a.ll LLVM :: ExecutionEngine/MCJIT/multi-module-sm-pic-a.ll LLVM :: ExecutionEngine/MCJIT/remote/cross-module-sm-pic-a.ll LLVM :: ExecutionEngine/MCJIT/remote/multi-module-sm-pic-a.ll And one FAIL: Failing Tests (1): LLVM ::

In practice all Apple hardwares support misaligned accesses for single-register loads and stores. If a pointer is not aligned, LLVM should not use the double-register loads and stores. It should keep the two single-register loads instead of trying to optimize them as one unsupported double-register load. Note that this code compiled with GCC 4.2 runs perfectly whereas LLVM will produce a binary

Hi Bradley, I was doing some performance analysis for ARMv7 (cortex-a9) and I noticed that one of my benchmarks degraded by 93%. I have tracked the regression down to the following commit by you: / //commit 7c1b77248baaeafec5d6433c3d1da9a2e2b69595// //Author: Bradley Smith <bradley.smith at arm.com>// //Date: Mon Nov 16 11:10:19 2015 +0000// // [ARM] Introduce subtarget features per

--- src/kernel.ml | 2 ++ src/utils.ml | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/kernel.ml b/src/kernel.ml index 356ac4b..9b0e8a2 100644 --- a/src/kernel.ml +++ b/src/kernel.ml @@ -30,6 +30,8 @@ let patt_of_cpu host_cpu = | "ppc" | "powerpc" | "powerpc64" -> ["ppc"; "powerpc"; "powerpc64"] |

In R 3.3.2 detectCores() in package parallel reports 2 rather than 1 on Raspberry Pi B+ running Raspbian. (This report is just 'for the record'. The model is superseded and I think no longer produced.) The problem seems to be caused by grep processor /proc/cpuinfo processor : 0 model name : ARMv6-compatible processor rev 7 (v6l) (On Raspberry Pi 2 and 3 there is no error because