Displaying 20 results from an estimated 200 matches similar to: "[LLVMdev] Reserved call frame"
2016 Jun 29
0
avx512 JIT backend generates wrong code on <4 x float>
Hi Frank,
I recommend trying trunk LLVM. AVX-512 development has been very active recently.
-Hal
----- Original Message -----
> From: "Frank Winter via llvm-dev" <llvm-dev at lists.llvm.org>
> To: "LLVM Dev" <llvm-dev at lists.llvm.org>
> Sent: Wednesday, June 29, 2016 2:41:39 PM
> Subject: [llvm-dev] avx512 JIT backend generates wrong code on <4
2016 Jun 30
1
avx512 JIT backend generates wrong code on <4 x float>
Hi Hal!
Thanks, but unfortunately it didn't help. The exact same assembler
instructions are generated for both 3.8 (yesterday) and trunk (from today).
So, this really looks like a bug.
Best,
Frank
On 06/29/2016 03:48 PM, Hal Finkel wrote:
> Hi Frank,
>
> I recommend trying trunk LLVM. AVX-512 development has been very active recently.
>
> -Hal
>
> ----- Original
2016 Jun 29
2
avx512 JIT backend generates wrong code on <4 x float>
Hi!
When compiling the attached module with the JIT engine on an Intel KNL I
see wrong code getting emitted. I attach a complete exploit program
which shows the bug in LLVM 3.8. It loads and JIT compiles the module
and prints the assembler. I stumbled on this since the result of an
actual calculation was wrong. So, it's not only the text version of the
assembler also the machine
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
With LLVM 3.8 the JIT compiler engine generates an AVX512 instruction
although I target an 'avx2' CPU (intel Core I7).
I just downloaded the most recent 3.8 and still it happens.
It happens with this input module:
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define void @module_cFFEMJ(i64 %lo, i64 %hi, i64 %myId, i1 %ordered, i64
%start, i32* noalias align 32
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
On 06/23/2016 12:56 PM, Craig Topper wrote:
> Can you check what value "getHostCPUName" returned?
getHostCPUName() = skylake
>
> On Thu, Jun 23, 2016 at 9:53 AM, Frank Winter via llvm-dev
> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>
> With LLVM 3.8 the JIT compiler engine generates an AVX512
> instruction although I
2003 Jun 27
2
Probs with smbfs
Hi all
I am having trouble with my SMBFS and it is the following
Every time I try to connect to other machine in my network, throught the command MOUNT, the folowing ERROR appears. I've already tried to see the manpage but i had not success.
[root@backup_sp bin] mount -t smbfs //sarq/c /mnt/windows
Password:
ERROR: smbfs filesystem not supported by the kernel
Please refer to the smbnt (8)
2014 Mar 12
2
[LLVMdev] Autovectorization questions
Hi,
I'm reading "http://llvm.org/docs/Vectorizers.html" and have few question.
Hope someone has answers on it.
The Loop Vectorizer can vectorize code that becomes a sequence of scalar
instructions that scatter/gathers memory. (
http://llvm.org/docs/Vectorizers.html#scatter-gather)
int foo(int *A, int *B, int n, int k) {
for (int i = 0; i < n; ++i)
A[i*7] += B[i*k];
}
I
2013 Oct 30
1
[LLVMdev] Optimization bug - spurious shift in partial word test
In the situation where a partial word is tested, lets say >0, by shifting
left to get the sign bit into the msb and testing llvm is inserting a
spurious right shift instruction.
For example this IR:
...
%0 = load i64* %a.addr, align 8
%shl = shl i64 %0, 28
%cmp = icmp sgt i64 %shl, 0
...
results in
...
shlq $28, %rdi
sarq $28, %rdi ; <<< spurious shift
2015 Jul 24
0
[LLVMdev] SIMD for sdiv <2 x i64>
------------------------------------ IR
------------------------------------------------------------------
if.then.i.i.i.i.i.i: ; preds = %if.then4
%S25_D = zext <2 x i32> %splatLDS17_D.splat to <2 x i64>
%umul_with_overflow.i.iS26_D = shl <2 x i64> %S25_D, <i64 3, i64 3>
%extumul_with_overflow.i.iS26_D = extractelement <2 x i64>
2015 Jul 24
1
[LLVMdev] SIMD for sdiv <2 x i64>
This snippet of IR is interesting:
%sub.ptr.div.iS37_D = sdiv <2 x i64> %sub.ptr.sub.iS36_D, <i64 24,
i64 24>
%cmp10S38_D = icmp ugt <2 x i64> %sub.ptr.div.iS37_D,
%splatInsMapS1_D.splat
%zextS39_D = sext <2 x i1> %cmp10S38_D to <2 x i64>
%BCS39_D = bitcast <2 x i64> %zextS39_D to i128
%mskS39_D = icmp ne i128 %BCS39_D, 0
br i1 %mskS39_D,
2019 Dec 23
1
[PATCH 0/8] Convert the intel iommu driver to the dma-iommu api
On 2019-12-23 10:37 am, Jani Nikula wrote:
> On Sat, 21 Dec 2019, Tom Murphy <murphyt7 at tcd.ie> wrote:
>> This patchset converts the intel iommu driver to the dma-iommu api.
>>
>> While converting the driver I exposed a bug in the intel i915 driver
>> which causes a huge amount of artifacts on the screen of my
>> laptop. You can see a picture of it here:
2019 Dec 23
0
[PATCH 0/8] Convert the intel iommu driver to the dma-iommu api
On Sat, 21 Dec 2019, Tom Murphy <murphyt7 at tcd.ie> wrote:
> This patchset converts the intel iommu driver to the dma-iommu api.
>
> While converting the driver I exposed a bug in the intel i915 driver
> which causes a huge amount of artifacts on the screen of my
> laptop. You can see a picture of it here:
>
2020 May 29
0
[PATCH 0/8] Convert the intel iommu driver to the dma-iommu api
On Thu, May 28, 2020 at 06:00:44PM -0600, Logan Gunthorpe wrote:
> > This issue is most likely in the i915 driver and is most likely caused by the driver not respecting the return value of the dma_map_ops::map_sg function. You can see the driver ignoring the return value here:
> >
2001 Mar 07
1
Minor bug in maketitle.pl (with bug correction) (PR#864)
Full_Name: Henrik Bengtsson
Version: rw1022
OS: Windows Me
Submission from: (NULL) (216.175.126.55)
When ${R_HOME}/share/perl/maketitle.pl tries to generate a TITLE that is longer
than $lc-3 (=13) characters long, it repeats the package name on line two.
Example: Now it generates an output like:
com.braju.graphics
com.braju.graphics Bla bla bla...
But, I believe it should
2014 Mar 12
4
[LLVMdev] Autovectorization questions
In order to vectorize code like this LLVM needs to prove that “A[i*7]” does not wrap in the address space. It fails to do so and so LLVM doesn’t vectorize this loop even if we try to force it.
The following loop will be vectorized if we force it:
int foo(int * A, int * B, int n, int k) {
for (int i = 0; i < 1024; ++i)
A[i] += B[i*k];
}
So will this loop:
int foo(int * restrict A, int
2020 Aug 26
0
[PATCH 0/8] Convert the intel iommu driver to the dma-iommu api
Hi Tom,
On 2019-12-21 15:03, Tom Murphy wrote:
> This patchset converts the intel iommu driver to the dma-iommu api.
>
> While converting the driver I exposed a bug in the intel i915 driver which causes a huge amount of artifacts on the screen of my laptop. You can see a picture of it here:
> https://github.com/pippy360/kernelPatches/blob/master/IMG_20191219_225922.jpg
>
>
2017 Jul 31
2
Segmentation fault in matcher/queryoptimiser
Since a couple of weeks we are experiencing occasional segmentation
faults within Xapian 1.5. We can't reproduce the crashes, but we have
strong hints that they are due to memory corruption. We have narrowed
down our root cause analysis to phrase searches on multi-databases that
fail on reading the `hint` field in the`QueryOptimiser`class [1].
We'd appreciate any hints on how to fix this.
2015 Jul 27
3
[LLVMdev] i1* function argument on x86-64
I am running into a problem with 'i1*' as a function's argument which
seems to have appeared since I switched to LLVM 3.6 (but can have other
source, of course). If I look at the assembler that the MCJIT generates
for an x86-64 target I see that the array 'i1*' is taken as a sequence
of 1 bit wide elements. (I guess that's correct). However, I used to
call the function
2011 Jul 01
0
[LLVMdev] LLVM and managed languages
Hi Talin,
I have some questions below. If these topics have already been discussed in earlier threads, kindly point me there. I'm aware of your GC proposal, but the rest is new to me.
On Jul 1, 2011, at 11:05 AM, Talin wrote:
> Garbage collection is still way too difficult. The biggest problem is the inability to track SSA values - it requires the frontend to generate very inefficient and
2020 Jul 09
2
Understand alias-analysis results
Hi again!
Replying in chronological order:
> On Thu, Jul 9, 2020 at 6:51 PM Shuai Wang <wangshuai901 at gmail.com
> <mailto:wangshuai901 at gmail.com>> wrote:
>
> Hey Matt,
>
> That's awesome. Thank you very much for all the information and
> clarification! Just a few follow up questions. Could you kindly shed
> some lights on it? Thank