Displaying 20 results from an estimated 7000 matches similar to: "[LLVMdev] Some questions on SelectionDAG"
2011 Sep 07
0
[LLVMdev] Fwd: Some questions on SelectionDAG
Thanks for all replies, they have been very helpful!
Note: Sorry, i forgot to group reply....
---------- Forwarded message ----------
From: Duncan Sands <baldrick at free.fr>
Date: 2011/9/4
Subject: Re: [LLVMdev] Some questions on SelectionDAG
To: Zakk <zakk0610 at gmail.com>
Hi Zak,
Therefore, after the LegalizeType phase, maybe SelectionDAG have
> unsupported
> type
[LLVMdev] [PATCH] fix a "jump to case label crosses initialization of llvm::MVT::ValueType VT" error
2007 Jul 14
1
[LLVMdev] [PATCH] fix a "jump to case label crosses initialization of llvm::MVT::ValueType VT" error
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- llvm.orig/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2007-07-14
16:59:23.000000000 +0200
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2007-07-14
16:59:52.000000000 +0200
@@ -696,7 +696,7 @@
}
}
break;
- case ISD::EH_RETURN:
+ case ISD::EH_RETURN: {
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
Hi,
For my research, I need to reshape the current ARM backend to support
armv2a. Zero-extend half word load (ldrh) is not supported by armv2a, so I
need to make the code generation to not generate ldrh instructions. I want
to replace all those instances with a 32-bit load (ldr) and then and the
result with 0xffff to mask out the upper bits.
These are the modifications that I have made to
2015 Mar 03
3
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
I'm curious about this code in ReduceLoadWidth (and in DAGCombiner in
general):
if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
return SDValue
<http://llvm.org/docs/doxygen/html/classllvm_1_1SDValue.html>();
LegalOperations is false for the first pre-legalize pass and true for the
post-legalize pass. The first pass is target-independent yes? So that makes
sense.
2009 Jun 11
0
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
On Jun 8, 2009, at 2:42 PM, robert muth wrote:
> On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com>
> wrote:
>>
>> On Jun 7, 2009, at 6:59 AM, robert muth wrote:
>>
>>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com>
>>> wrote:
>>>> +cl::opt<std::string>
2009 Jun 08
2
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>
> On Jun 7, 2009, at 6:59 AM, robert muth wrote:
>
>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com>
>> wrote:
>>> +cl::opt<std::string> FlagJumpTableSection("jumptable-section",
>>> +
2010 Oct 02
1
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
Hi,
>> DAGCombiner::visitBRCOND() has code:
>>
>> SDValue N1 = N->getOperand(1);
>> SDValue N2 = N->getOperand(2);
>>
>> ...
>>
>> SDNode *Trunc = 0;
>> if (N1.getOpcode() == ISD::TRUNCATE&& N1.hasOneUse()) {
>> // Look past truncate.
>> Trunc = N1.getNode();
>> N1 = N1.getOperand(0);
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
Per subject, this patch adding an additional pass to handle vector
operations; the idea is that this allows removing the code from
LegalizeDAG that handles illegal types, which should be a significant
simplification. There are still some issues with this patch, but does
the approach look sane?
-Eli
-------------- next part --------------
Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
2013 Aug 08
3
[LLVMdev] Storage-Only Register Class?
Is there a way to define a register class that is storage-only? I want to
have an i8 register class that I can use for loads/stores/converts, but
that does not support arithmetic.
It seems addOperationAction(ISD::ADD, MVT::i8, Promote) and
SetPromotedToType(ISD::ADD, MVT::i8, MVT::i16) are not sufficient, as the
legalizer just looks at whether or not the underlying type is legal (which
it is).
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
Bill Wendling wrote:
> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>
>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>
>>> Our architecture has 1-bit boolean predicate registers.
>>>
>>> I've defined comparison
>>>
>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set
2007 Feb 12
2
[LLVMdev] bitconvert for multi-typed RegisterClasses
Hi All,
I'm working on a back end for an architecture that makes use of multi-
typed register classes.
def MR: RegisterClass<"namespace", [type1, type2, ... ], ... >
When running some preliminary tests I found that the instruction
selector refused to select certain ops (specifically stores) for some
instructions when the operand type wasn't the first type for the
2015 Mar 03
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
1) It's crashing because LD1 is produced due to LegalOperations=false in
pre-legalize pass. Then Legalization does not know how to handle it so it
asserts on a default case. I don't know if it's a reasonable expectation or
not but we do not have support for it. I have not tried
overriding shouldReduceLoadWidth.
2) I see, that makes sense to some degree, I'm curious if you can
2012 Aug 15
0
[LLVMdev] More Back-End Porting Troubles
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Fabian Scheler
> Sent: Wednesday, August 15, 2012 9:12 AM
> To: LLVM Developers Mailing List
> Subject: [LLVMdev] More Back-End Porting Troubles
>
> Hi LLVM-Folks,
>
> as mentioned in an earlier post
>
2008 Oct 11
2
[LLVMdev] api changes in llvm 2.4
In the 2.3 release, we included a list of the major LLVM API changes.
If you are working on upgrading your code from 2.3 to 2.4, I'd
appreciate it if you could compile a list of the major stumbling
blocks you have, so that others can benefit from your experience.
Please send any info to the list, thanks!
-Chris
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I fixed the bug reported in the previous post on this thread
(<<llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&,
llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <=
MMO->getSize() && "Size mismatch!"' failed.>>)
The problem with this strange error reported comes from
2007 Feb 12
0
[LLVMdev] bitconvert for multi-typed RegisterClasses
On Feb 12, 2007, at 1:41 AM, Christopher Lamb wrote:
>
> selector refused to select certain ops (specifically stores) for some
> instructions when the operand type wasn't the first type for the
> register class. After some digging around I seem to have solved the
> problem by creating bitconvert patterns between the types in the
> register class like the following:
>
>
2012 Aug 15
5
[LLVMdev] More Back-End Porting Troubles
Hi LLVM-Folks,
as mentioned in an earlier post
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-July/051677.html) I
am currently working on a Back-End for the TriCore processor.
Currently, I am struggling as LLVM could not select zext and load, for
instance, so some of the testcases in test/CodeGen/Generic are not
successfully compiled by my back-end.
Furthermore, I am completely puzzled by the
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote:
> Bill Wendling wrote:
>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>>
>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>
>>>> Our architecture has 1-bit boolean predicate registers.
>>>>
>>>> I've defined comparison
>>>>
>>>> def
2009 Jun 29
2
[LLVMdev] Inserting nodes into SelectionDAG (X86)
Sorry to ask again, but I still can't get it right.
The following code compiles and runs, but produces no instructions:
Ops.push_back(DAG.getRegister(X86::EAX, MVT::i32));
Ops.push_back(DAG.getConstant(1, MVT::i32));
DAG.getNode(ISD::ADD, DAG.getVTList(MVT::i32), &Ops[0], Ops.size());
I reckon that has something to do with the fact that I am not using the
Chain object. But as soon
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
Hello.
I'm having problems at instruction selection with my back end with the following
basic-block due to a vector add with immediate constant vector (obtained by vectorizing a
simple C program doing vector sum map):
vector.ph: ; preds = %vector.memcheck50
%.splatinsert = insertelement <8 x i64> undef, i64 %i.07.unr, i32 0