similar to: [LLVMdev] Why int variable get promoted to i64

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Why int variable get promoted to i64"

2011 Aug 19
0
[LLVMdev] Why int variable get promoted to i64
Because you are compiling for a 64-bit system which uses LP64. As such pointers are 64-bit in length... while integers remain defined as 32-bits. So why 64-bits for i? The compiler is treating index variables special. Index variables need to be able to index 64-bits of space and in fact you'll see the promotion here: for.body: ; preds = %for.cond
2011 Aug 19
0
[LLVMdev] Why int variable get promoted to i64
> Because you are compiling for a 64-bit system which uses LP64. As such pointers are 64-bit in length... while integers remain defined as 32-bits. > > So why 64-bits for i? The compiler is treating index variables special. Index variables need to be able to index 64-bits of space and in fact you'll see the promotion here: > > for.body:
2019 Nov 10
2
Reassociation is blocking a vectorization
Hi Devs, I am looking at the bug https://bugs.llvm.org/show_bug.cgi?id=43953 and found that following piece of ir %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom %0 = load float, float* %arrayidx, align 4, !tbaa !2 %arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom %1 = load float, float* %arrayidx2, align 4, !tbaa !2 %sub = fsub fast float %0, %1
2017 Aug 08
2
[ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
Hi all, I'm looking into resolving a FIXME in the LoopDataPrefetch (and FalkorMarkStridedAccesses) pass by marking both of these passes as preserving the ScalarEvolution analysis. Unfortunately, when this change is made, LSR will generate different code. One of the root causes seems to be that SCEV will return different nsw/nuw flags for the same Value, depending on what order the
2014 Feb 19
2
[LLVMdev] better code for IV
Hi Andrew, The issue below refers to LSR, so I'll appreciate your feedback. It also refers to instruction combining and might impact backends other than X86, so if you know of others that might be interested you are more than welcome to add them. Thanks, Anat _____________________________________________ From: Shemer, Anat Sent: Tuesday, February 18, 2014 15:07 To: 'llvmdev at
2015 Nov 12
4
Fwd: asan for allocas on powerpc64
(Resending with the correct mailing list address.) Hi, Currently test/asan/TestCases/alloca_vla_interact.cc is XFAILed for powerpc64. I've had a look at why it doesn't work. I think the only problem is in the call to __asan_allocas_unpoison that is inserted at the end of the "for" loop (just before a stackrestore instruction). The call function is created something like this
2015 Aug 22
3
loop unrolling introduces conditional branch
Hi, Mehdi, For example, I have this very simple source code: void foo( int n, int array_x[]) { for (int i=0; i < n; i++) array_x[i] = i; } After I use "clang -emit-llvm -o bc_from_clang.bc -c try.cc", I get bc_from_clang.bc. With my code (using LLVM IRbuilder API), I get bc_from_api.bc. Attachment please find thse two files. I also past the IR here.
2015 Aug 22
2
loop unrolling introduces conditional branch
Thanks for your point that out. I just add DataLayout in my code such as "mod->setDataLayout("e-m:e-i64:64-f80:128-n8:16:32:64-S128");", still no luck. I'm really confused about this. Do I need to add more passes before -loop-unroll? On Sat, Aug 22, 2015 at 11:36 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Aug 22, 2015, at 7:27 AM, Xiangyang
2019 Feb 21
2
If there are some passes in LLVM do the opposite of the SROA(Scalar Replacement of Aggregates) pass
Hi LLVM developers, We tried to find if there are some passes in LLVM do the opposite of the SROA(Scalar Replacement of Aggregates) pass, but did not find one. Do we have this kind of pass to bring back the structure type? Or this is done separately in any transformation passes? Thanks, Lin-Ya -------------- next part -------------- An HTML attachment was scrubbed... URL:
2016 Feb 02
5
Particular type of loop optimization
Dear LLVMers, I am trying to implement a particular type of loop optimization, but I am having problems with global variables. To solve this problem, I would like to know if LLVM has some pass that moves loads outside loops. I will illustrate with an example. I want to transform this code below. I am writing in C for readability, but I am analysing LLVM IR: int *vectorE; void foo (int n) {
2015 Nov 17
3
asan for allocas on powerpc64
Hi! Sorry for delay, just returned from vacation. On 12/11/15 23:44, Kostya Serebryany via llvm-dev wrote: > +Maxim and Yuri, as I think this is their code. > > On Thu, Nov 12, 2015 at 3:02 AM, Jay Foad <jay.foad at gmail.com > <mailto:jay.foad at gmail.com>> wrote: > > (Resending with the correct mailing list address.) > > Hi, > > Currently
2013 Feb 05
3
[LLVMdev] Vectorizing global struct pointers
Hi all, One of the reasons the Livermore Loops couldn't be vectorized is that it was using global structures to hold the arrays. Today, I'm investigating why is that so and how to fix it. My investigation brought me to LoopVectorizationLegality::canVectorizeMemory(): if (WriteObjects.count(*it)) { DEBUG(dbgs() << "LV: Found a possible read/write reorder:"
2017 Jun 20
2
Problem with shortestPath in igraph and qgraph
hello, I have a graph and i use qgraph package to calculate centrality parameters. Now I want to know the maximum value of shortest path for each vertex with discarding the Inf value in short pathes. For this I use the ShortestPathLengths of centrality function in qgraph. but when I want to get the maximum the result is wrong. here is my code: cen<-centrality(Q)
2016 Aug 25
2
InstList insert depreciated?
Jon, > You want: > TaintVar->insertAfter(FirstI); This worked! Thank you. On Thu, Aug 25, 2016 at 9:38 AM, Jonathan Roelofs <jonathan at codesourcery.com> wrote: > > > On 8/25/16 7:01 AM, Shehbaz Jaffer via llvm-dev wrote: >> >> I tried an alternative way of adding instruction by first getting the >> first instruction of the basic block, and then
2016 Aug 25
2
InstList insert depreciated?
Hi llvm-devel, I have migrated my codebase from llvm-3.6 to llvm 3.8.1-stable. Although I was able to resolve most of the problems, I am facing issues resolving the following: To insert an instruction immediately after the first instruction within a basic block, I first get all instructions in my basic block in an instruction container list. Once that is done, I insert my new instruction in the
2017 Jun 21
0
Problem with shortestPath in igraph and qgraph
Hard to follow data analysis without data. Try making your example reproducible [1][2][3] and post in plain text (a setting in your emailer). Read the Posting Guide mentioned in the footer to avoid other posting pitfalls. [1] http://stackoverflow.com/questions/5963269/how-to-make-a-great-r-reproducible-example [2] http://adv-r.had.co.nz/Reproducibility.html [3]
2017 Dec 06
2
[AMDGPU] Strange results with different address spaces
> On Dec 6, 2017, at 02:28, Haidl, Michael <michael.haidl at uni-muenster.de> wrote: > > The IR goes through a backend agnostic preparation phase that brings it into SSA from and changes the AS from 0 to 1. This sounds possibly problematic to me. The IR should be created with the correct address space to begin with. Changing this in the middle sounds suspect. > After this
2013 Jan 29
3
[LLVMdev] [PATCH] parallel loop awareness to the LoopVectorizer
On Jan 29, 2013, at 12:51 AM, Tobias Grosser <tobias at grosser.es> wrote: > > # ignore assumed dependences. > for (i = 0; i < 4; i++) { > tmp1 = A[3i+1]; > tmp2 = A[3i+2]; > tmp3 = tmp1 + tmp2; > A[3i] = tmp3; > } > > Now I apply for whatever reason a partial reg2mem transformation. > > float tmp3[1]; > > # ignore assumed
2004 Jul 03
2
Multiple E1s over TDMoE?
When I was trying to run mutiple E1s over TDMoE, the zaptel would drivers complain about too little memory, whenever I added more than 31 channels. Requesting 62 channels in a dynamic span gave me ... span creation failed: Cannot allocate memory upon loading the zaptel drivers. How would you go about running, 8 or 16 say, E1s over TDMoE? Would you create multiple dynamic spans or just one large
2017 Aug 08
2
[ScalarEvolution][SCEV] no-wrap flags dependent on order of getSCEV() calls
On 8/8/2017 1:37 PM, Friedman, Eli wrote: > On 8/8/2017 10:22 AM, Geoff Berry via llvm-dev wrote: >> Hi all, >> >> I'm looking into resolving a FIXME in the LoopDataPrefetch (and FalkorMarkStridedAccesses) pass by marking both of these passes as preserving the ScalarEvolution analysis. Unfortunately, when this change is made, LSR will generate different code. One of the