similar to: [LLVMdev] Tying an instruction to a specific set of registers

Jim, Thanks for the hints. Does LLVM allow allocation of the same register across register classes? For example, in the ARM backend, can an instruction write to R0 when it is part of register class tGPR, but then use R0 in the next instruction as a source register from the rGPR class? If LLVM can do this, then this will work. Micah > -----Original Message----- > From: Jim Grosbach

Hi Micah, You can just create a new register class that only contains the registers you want and use that for the instruction. The set theoretic operators for register class definition make this very easy. See the ARM backend definitions of GPRnopc, rGPR, etc.. for examples. -Jim On Aug 16, 2011, at 9:18 AM, Villmow, Micah wrote: > Is there a way in tablegen to specify that a certain

I have a register hierarchy that looks like a binary tree. v4 -> {v2, v2} -> {s, s}{s, s}(or, {x, y}, {z, w}) I have an instruction that can access the 2nd and/or 4th scalar and an instruction that can access the 1st and/or 3rd scalar. What I need to do is that given the first scalar, I need to be able to select the 2nd scalar, or/and given the 3rd, select the 4th. I define a sibling

Hi Micah, This sounds somewhat similar to what ARM uses for the stride-by-two vector load instructions. For example, Tuples2DSpc. While not exactly what you're looking for, perhaps something along those lines would work? -Jim On Jul 17, 2012, at 3:24 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > I have a register hierarchy that looks like a binary tree. >

> -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Monday, November 08, 2010 10:41 AM > To: Villmow, Micah > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Creating tablegen patterns for intrinsics with > no return value. > > > On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > > > I have intrinsic with no

On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Hi Micah, >From your description it sounds like machine dead code elimination is

I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Here is my profile/node/pattern. Profile: def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ SDTCisPtrTy<0>, SDTCisVT<1, i32>,

I'm working on intrinsics for my backend and require intrinsic overloading. Is this supported? If so, are there any examples? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100629/04db85ea/attachment.html>

On Tue, Jun 29, 2010 at 12:16 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I'm working on intrinsics for my backend and require intrinsic overloading. > Is this supported? If so, are there any examples? Some of the ARM NEON intrinsics are overloaded. -Eli

If I don't bring in TargetData, then there is no way for me to verify the address space size in the verifier or in the auto-upgrade mechanisms. > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Thursday, September 20, 2012 2:32 PM > To: Villmow, Micah > Cc: Chris Lattner; Mon Ping Wang; llvm-commits at cs.uiuc.edu; > llvmdev at

Ping! > -----Original Message----- > From: Villmow, Micah > Sent: Tuesday, September 18, 2012 4:12 PM > To: 'Chris Lattner'; 'Mon Ping Wang' > Cc: 'llvm-commits at cs.uiuc.edu'; 'llvmdev at cs.uiuc.edu' > Subject: RE: [LLVMdev] Proposal: New IR instruction for casting between > address spaces > > Resending since I got an error. >

> -----Original Message----- > From: Mon P Wang [mailto:monping at apple.com] > Sent: Wednesday, September 12, 2012 1:12 PM > To: Villmow, Micah > Cc: Dan Gohman; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Proposal: New IR instruction for casting between > address spaces > > Hi, > > On Sep 11, 2012, at 2:30 PM, Villmow, Micah wrote: > > > > >

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

On Thu, 20 Sep 2012 15:34:52 -0700 Eli Friedman <eli.friedman at gmail.com> wrote: > On Thu, Sep 20, 2012 at 3:30 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: > > If I don't bring in TargetData, then there is no way for me to > > verify the address space size in the verifier or in the > > auto-upgrade mechanisms. > > And that's why I

> -----Original Message----- > From: Dan Gohman [mailto:gohman at apple.com] > Sent: Tuesday, September 11, 2012 1:28 PM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Proposal: New IR instruction for casting between > address spaces > > On Sep 11, 2012, at 1:03 PM, "Villmow, Micah" <Micah.Villmow at amd.com> > wrote: >

On Thu, Sep 20, 2012 at 3:30 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > If I don't bring in TargetData, then there is no way for me to verify the address space size in the verifier or in the auto-upgrade mechanisms. And that's why I didn't like this approach in the first place. -Eli >> -----Original Message----- >> From: Eli Friedman

> -----Original Message----- > From: Mon Ping Wang [mailto:monping at apple.com] > Sent: Thursday, September 13, 2012 1:55 AM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Proposal: New IR instruction for casting between > address spaces > > > On Sep 12, 2012, at 2:45 PM, "Villmow, Micah" <Micah.Villmow at amd.com> >

On Sep 12, 2012, at 2:45 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > > >> -----Original Message----- >> From: Mon P Wang [mailto:monping at apple.com] >> Sent: Wednesday, September 12, 2012 1:12 PM >> To: Villmow, Micah >> Cc: Dan Gohman; llvmdev at cs.uiuc.edu >> Subject: Re: [LLVMdev] Proposal: New IR instruction for

We can't add a circular dependency between Target and VMCore. -Eli On Thu, Sep 20, 2012 at 8:21 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Ping! > >> -----Original Message----- >> From: Villmow, Micah >> Sent: Tuesday, September 18, 2012 4:12 PM >> To: 'Chris Lattner'; 'Mon Ping Wang' >> Cc: 'llvm-commits at

> -----Original Message----- > From: Chris Lattner [mailto:clattner at apple.com] > Sent: Thursday, September 13, 2012 11:53 PM > To: Mon Ping Wang > Cc: Villmow, Micah; llvmdev at cs.uiuc.edu Mailing List > Subject: Re: [LLVMdev] Proposal: New IR instruction for casting between > address spaces > > > On Sep 13, 2012, at 5:55 PM, Mon Ping Wang <monping at