similar to: [LLVMdev] Order of code generation

Displaying 20 results from an estimated 4000 matches similar to: "[LLVMdev] Order of code generation"

2011 Aug 12
2
[LLVMdev] Order of code generation
I need help with visualizing graphs before and after instruction selection. The llc options listed in the docs do not work as specified. -Omer 2011/8/8 Rafael Ávila de Espíndola <rafael.espindola at gmail.com> > On 08/06/2011 02:40 AM, Sanjoy Das wrote: > > Hi! > > > > I have a DAG (attached), which, according to me, should result in the > > code for
2011 Aug 08
0
[LLVMdev] Order of code generation
On 08/06/2011 02:40 AM, Sanjoy Das wrote: > Hi! > > I have a DAG (attached), which, according to me, should result in the > code for coroutine_make be generated _before_ the ret. > > However, it seems that the corresponding EmitInstrWithCustomInserter is > being called /after/ the RET instruction has already been emitted. That is strange, from the dump it looks like all the
2011 Aug 13
2
[LLVMdev] Order of code generation
On 13/08/11 00:01, Cameron Zwarich wrote: > They do work if you have GraphViz binaries in your path when you configure LLVM. I think you also need to build with assertions enabled. Ciao, Duncan. > > Cameron > > On Aug 12, 2011, at 2:59 PM, محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ wrote: > >> I need help with visualizing graphs before and after instruction selection. >> The llc options
2011 Aug 12
0
[LLVMdev] Order of code generation
They do work if you have GraphViz binaries in your path when you configure LLVM. Cameron On Aug 12, 2011, at 2:59 PM, محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ wrote: > I need help with visualizing graphs before and after instruction selection. > The llc options listed in the docs do not work as specified. > > -Omer > > 2011/8/8 Rafael Ávila de Espíndola <rafael.espindola at gmail.com> > On
2011 Aug 15
0
[LLVMdev] Order of code generation
How do I enable the assertions when building ? I am using 2.9, the current version, and when I use the standard build llc does not give me the view-*-dags options. -Omer On Sat, Aug 13, 2011 at 1:50 AM, Duncan Sands <baldrick at free.fr> wrote: > On 13/08/11 00:01, Cameron Zwarich wrote: > > They do work if you have GraphViz binaries in your path when you > configure LLVM.
2011 Aug 15
2
[LLVMdev] Order of code generation
On 15/08/11 13:12, محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ wrote: > How do I enable the assertions when building ? > I am using 2.9, the current version, and when I use the standard build llc does > not give me the view-*-dags options. Configure with --enable-assertions Ciao, Duncan. > > -Omer > > On Sat, Aug 13, 2011 at 1:50 AM, Duncan Sands <baldrick at free.fr > <mailto:baldrick at
2011 Aug 15
0
[LLVMdev] Order of code generation
After enabling assertions and recompilation I still get this error. ~/bin/llvm$ llc -view-isel-dags t3.bc llc: Unknown command line argument '-view-isel-dags'. Try: 'llc -help' llc: Did you mean '-fast-isel-abort'? and I see the view-edge bundles option but get the following error. ~/bin/llvm$ llc -view-edge-bundles t3.bc Writing
2012 May 03
2
[LLVMdev] Inserting a branch in PPCTargetLowering::LowerFormalArguments_SVR4
Hello, The current code in PPCTargetLowering::LowerFormalArguments_SVR4 contains a FIXME over the code which saves the live floating-point registers to the stack. The FIXME states that this should only be done if CR bit 6 is set. I've been told that the lack of this check is preventing clang/LLVM from compiling a functional FreeBSD kernel on PPC. Is is possible to insert another branch in
2012 Jul 20
2
[LLVMdev] Help with Instruction Expansion on Mips
Hi everyone, I am a newbie to LLVM. I am trying to ban some of instructions in Mips Instruction, for example, lh, lhu, sh, and etc. I have tried to directly comment lh, lhu, and sh to make llvm not to choose these instruction when compiling, however, it usually cause a 'can not select ...' error when using 'short' data type in source code. Then I tried to expand these instructions
2008 Feb 20
0
[LLVMdev] compare and swap
The current *hack* solution is to mark your pseudo instruction with usesCustomDAGSchedInserter = 1. That allows the targets to expand it at scheduling time by providing a EmitInstrWithCustomInserter() hook. You can create new basic blocks then. Evan On Feb 19, 2008, at 4:51 PM, Andrew Lenharth wrote: > I was working on compare and swap and ran into the following problem. > Several
2008 Feb 20
1
[LLVMdev] compare and swap
On 2/19/08, Evan Cheng <evan.cheng at apple.com> wrote: > The current *hack* solution is to mark your pseudo instruction with > usesCustomDAGSchedInserter = 1. That allows the targets to expand it > at scheduling time by providing a EmitInstrWithCustomInserter() hook. > You can create new basic blocks then. I guess that can work in the short term. It just seems wasteful for
2009 Mar 22
0
[LLVMdev] Implementing select_cc without cmov
someguy wrote: > Hi All, > > I need to implement select_cc as a "cmp; mov rX,1; brcond cnd, END; > mov rX,0; END:" sequence. > > Chris mentioned that the PPC code (as well as the x86 SSE code) does > this, but I can't seem to find it. > > What I really need to kmow is how to insert the branch/label pair at > instruction selection phase. > > Anyone
2012 May 10
0
[LLVMdev] Inserting a branch in PPCTargetLowering::LowerFormalArguments_SVR4
I hate to be bothersome, but can someone please comment on this? Thanks again, Hal On Thu, 3 May 2012 14:49:04 -0500 Hal Finkel <hfinkel at anl.gov> wrote: > Hello, > > The current code in PPCTargetLowering::LowerFormalArguments_SVR4 > contains a FIXME over the code which saves the live floating-point > registers to the stack. The FIXME states that this should only be done
2006 Sep 23
6
Connection to backgroundrb is lost when exiting action method
Hey. I have a very annoying problem, and was wondering what is wrong. Suppose I have backgroundrb running, and then I have an action in some controller. In the action I define a worker. When leaving the action, suddenly the connection to backgroundrb is lost: DRb URI: druby://localhost:22222 Pid: 3976 Autostart... done druby://localhost:42531 - #<Errno::EBADF: Bad file descriptor -
2012 May 10
2
[LLVMdev] Inserting a branch in PPCTargetLowering::LowerFormalArguments_SVR4
Hi Hal, For lowering code that requires inserting branches, you need to use a custom inserter, yes. Theoretically, that does indeed sound like what you want to do here. It's complicated by the general structure of argument passing, though. In particular, there's lots of assumptions about the call sequence stuff. I don't know if things are smart enough (EH in particular worries me) to
2020 Jun 26
2
How to implement load/store for vector predicate register
Hi, I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands. If I use virtual registers, do I need to mark them as "early clobber"? I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend. What is the effect of marking a
2012 Jan 25
2
[LLVMdev] Best way to interface with MSVC _ftol2 runtime function for fptoui?
On Jan 24, 2012, at 2:30 PM, Joe Groff wrote: > On Fri, Jan 20, 2012 at 2:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> X86FloatingPoint.cpp with comments is all you get. > > Thanks for your help, Jakob. Attached is a first-pass attempt at a > patch. I don't want to post to -commits yet because I have no idea if > this is fully correct, but it seems
2012 Jul 20
0
[LLVMdev] Help with Instruction Expansion on Mips
why do you want to "ban" certain instructions? is this for some architectural variant? the compiler is trying to match patterns from the target independent part of the code generator. if you remove instructions, the compiler in many cases will no longer be able to match certain patterns and you will get thos "can not select" messages. On 07/20/2012 03:05 AM, Geraint Yang
2011 Jan 03
3
Distorted output in fixed-point AEC
Hi, I couldn't find a discussion that specifically addresses this, so here it is. I'm using Speex AEC in my mobile VoIP application to cancel speaker echo. The used version is 1.2rc1 from the website, and I'm compiling with fixed-point. On most occasions, the AEC works very well and cancels most of the echo (combined with the preprocessor). On some devices, where the microphone signal
2016 Nov 20
3
RFC: Insertion of nops for performance stability
Hi Hal, A pre-emit pass will indeed be preferable. I originally thought of it, too, however I could not figure out how can such a pass have an access to information on instruction sizes and block alignments. I know that for X86, at least, the branch relaxation is happening during the layout phase in the Assembler, where I plan to integrate the nop insertion such that the new MCPerfNopFragment