Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] llvm 3.0 svn and cfi_* directives"
2019 Feb 05
2
clang emits calls to consexpr function.
Hi Devs,
consider below testcase
$cat test.cpp
constexpr int product()
{
return 10*20;
}
int main()
{
const int x = product();
return 0;
}
$./clang test.cpp -std=c++11 -S
$./clang -v
clang version 9.0.0
Target: x86_64-unknown-linux-gnu
$cat test.s
main:
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq
2012 May 24
4
[LLVMdev] use AVX automatically if present
I wonder why AVX is not used automatically if available at the host
machine. In contrast to that, SSE41 instructions (like pmulld) are
automatically used if the host machine supports SSE41.
E.g.
$ cat avx.ll
define void @_fun1(<8 x float>*, <8 x float>*) {
_L1:
%x = load <8 x float>* %0
%y = load <8 x float>* %1
%z = fadd <8 x float> %x, %y
store
2014 May 11
2
[LLVMdev] [cfe-dev] Code generation for noexcept functions
On Sun, May 11, 2014 at 8:19 AM, Stephan Tolksdorf <st at quanttec.com> wrote:
> Hi,
>
> When clang/LLVM can't prove that a noexcept function only contains
> non-throwing code, it seems to insert an explicit exception handler that
> calls std::terminate. Why doesn't clang leave it to the eh personality
> function to call std::terminate when an exception is thrown
2012 Mar 02
0
[LLVMdev] how to annotate assembler
On 02.03.2012, at 09:20, Konstantin Vladimirov wrote:
> Hi,
>
> In GCC there is one useful option -dp (or -dP for more verbose output)
> to annotate assembler with instruction patterns, that was used when
> assembler was generated. For example:
The internal "-mllvm -show-mc-inst" option is probably as close as you can get.
$ clang -S -O0 test.c -mllvm -show-mc-inst -o
2012 Mar 02
3
[LLVMdev] how to annotate assembler
Hi,
In GCC there is one useful option -dp (or -dP for more verbose output)
to annotate assembler with instruction patterns, that was used when
assembler was generated. For example:
double
test(long long s)
{
return s;
}
gcc -S -dp -O0 test.c
test:
.LFB0:
.cfi_startproc
pushq %rbp # 18 *pushdi2_rex64/1 [length = 1]
.cfi_def_cfa_offset 16
movq %rsp, %rbp # 19 *movdi_1_rex64/2
2013 Jul 10
4
[LLVMdev] unaligned AVX store gets split into two instructions
I'm seeing a difference in how LLVM 3.3 and 3.2 emit unaligned vector loads
on AVX.
3.3 is splitting up an unaligned vector load but in 3.2, it was emitted as
a single instruction (details below).
In a matrix-matrix inner-kernel, I see a ~25% decrease in performance,
which seems to be due to this.
Any ideas why this changed? Thanks!
Zach
LLVM Code:
define <4 x double> @vstore(<4 x
2016 Jun 30
4
Help required regarding IPRA and Local Function optimization
Hello Mentors,
I am currently finding bug in Local Function related optimization due to
which runtime failures are observed in some test cases, as those test cases
are containing very large function with recursion and object oriented code
so I am not able to find a pattern which is causing failure. So I tried
following simple case to understand expected behavior from this
optimization.
Consider
2019 Aug 08
2
Suboptimal code generated by clang+llc in quite a common scenario (?)
I found a something that I quite not understand when compiling a common piece of code using the -Os flags.
I found it while testing my own backend but then I got deeper and found that at least the x86 is affected as well. This is the referred code:
char pp[3];
char *scscx = pp;
int tst( char i, char j, char k )
{
scscx[0] = i;
scscx[1] = j;
scscx[2] = k;
return 0;
}
The above gets
2012 May 24
0
[LLVMdev] use AVX automatically if present
On Thu, 24 May 2012, Pan, Wei wrote:
> Very likely AVX is not enabled in your llc. This feature was enabled
> just recently (late of April).
I forgot to mention that I am using recent LLVM-3.1 and in principle my
llc knows about avx as I have shown in the second example. But avx does
not seem to be used by default.
On Thu, 24 May 2012, Henning Thielemann wrote:
> $ llc -o - -mattr
2013 Feb 20
3
[LLVMdev] Is va_arg correct on Mips backend?
I didn't have Mips board. I compile as the commands and check the asm output as below.
1. Question:
The distance of caller arg[4] and arg[5] is 4 bytes. But the the callee get every
arg[] by 8 bytes offset (arg_ptr1+8 or arg_ptr2+8). I assume the #BB#4 and #BB#5 are the arg_ptr which is the pointer to access the stack arguments.
2. Question:
Stack memory 28($sp) has no initial value. If
2019 Jul 26
2
Stackmap offset computation on AArch64
Hi all,
I am trying to implement statepoints for the AArch64 target and I’m running into the issue where the following bitcode:
define i32 addrspace(1)* @test(i32 addrspace(1)* %ptr) gc "statepoint-example" {
entry:
call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @foo, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %ptr)
ret
2012 Jul 29
3
[LLVMdev] rotate
Nice!
Clever compiler..
On 07/28/2012 08:55 PM, Michael Gottesman wrote:
> I can get clang/llvm to emit a rotate instruction on x86-64 when compiling C by just using -Os and the rotate from Hacker's Delight i.e.,
>
> ======
> #include<stdlib.h>
> #include<stdint.h>
>
> uint32_t ror(uint32_t input, size_t rot_bits)
> {
> return (input>>
2013 Feb 20
0
[LLVMdev] Is va_arg correct on Mips backend?
Does it make a difference if you give the "-target" option to clang?
$ clang -target mips-linux-gnu ch8_3.cpp -o ch8_3.bc -emit-llvm -c
The .s file generated this way looks quite different from the one in your
email.
On Tue, Feb 19, 2013 at 5:06 PM, Jonathan <gamma_chen at yahoo.com.tw> wrote:
> I didn't have Mips board. I compile as the commands and check the asm
>
2012 Mar 28
2
[LLVMdev] Suboptimal code due to excessive spilling
Hi,
I have run into the following strange behavior and wanted to ask for
some advice. For the C program below, function sum() gets inlined in
foo() but the code generated looks very suboptimal (the code is an
extract from a larger program).
Below I show the 32-bit x86 assembly as produced by the demo page on
the llvm home page ("Output A"). As you can see from the assembly,
after
2017 Aug 21
3
DragonEgg for GCC v8.x and LLVM v6.x is just able to work
Hi LLVM and GCC developers,
My sincere thanks will goto:
* Duncan, the core developer of llvm-gcc and dragonegg
http://llvm.org/devmtg/2009-10/Sands_LLVMGCCPlugin.pdf
* David, the innovator and developer of GCC
https://dmalcolm.fedorapeople.org/gcc/global-state/requirements.html
and others who give me kind response for teaching me patiently and
carefully about how to migrate GCC v4.8.x to
2012 Jul 29
0
[LLVMdev] rotate
I can get clang/llvm to emit a rotate instruction on x86-64 when compiling C by just using -Os and the rotate from Hacker's Delight i.e.,
======
#include <stdlib.h>
#include <stdint.h>
uint32_t ror(uint32_t input, size_t rot_bits)
{
return (input >> rot_bits) | (input << ((sizeof(input) << 3) - rot_bits));
}
======
Then compile with (assuming you are on OS
2012 Apr 05
0
[LLVMdev] Suboptimal code due to excessive spilling
I don't know much about this, but maybe -mllvm -unroll-count=1 can be used as a workaround?
/Patrik Hägglund
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Brent Walker
Sent: den 28 mars 2012 03:18
To: llvmdev
Subject: [LLVMdev] Suboptimal code due to excessive spilling
Hi,
I have run into the following strange behavior
2014 Aug 08
4
[LLVMdev] Efficient Pattern matching in Instruction Combine
Hi Duncan, David, Sean.
Thanks for your reply.
> It'd be interesting if you could find a design that also treated these
> the same:
>
> (B ^ A) | ((A ^ B) ^ C) -> (A ^ B) | C
> (B ^ A) | ((B ^ C) ^ A) -> (A ^ B) | C
> (B ^ A) | ((C ^ A) ^ B) -> (A ^ B) | C
>
> I.e., `^` is also associative.
Agree with Duncan on including associative operation too.
2013 Sep 05
0
[LLVMdev] C int type for 48bits cpu
On Sep 5, 2013, at 3:37 AM, gamma_chen <gamma_chen at yahoo.com.tw> wrote:
> LLVM only support primitive type i32 and i64, no i48. The clang translate "C int type" to i32 too. My question is if a cpu is 48 bits register size, how to write the backend for 48 bits register architecture. Can someone help me with this problem?
I'm not LLVM expert, but I'm pretty sure your
2009 Aug 18
0
[LLVMdev] Build issues on Solaris
Hello, Nathan
> or if it should be a configure test, which might be safer. Are there
> any x86 platforms (other than apple) that don't need PLT-indirect calls?
Yes, mingw. However just tweaking the define is not enough - we're not
loading address of GOT into ebx before the call (on 32 bit ABIs) thus
the call will be to nowhere.
--
With best regards, Anton Korobeynikov
Faculty of