similar to: [LLVMdev] Avoiding load narrowing in DAGCombiner

Hi Eli, On 07/27/2011 04:59 PM, Eli Friedman wrote: > On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson > <johnso87 at crhc.illinois.edu> wrote: >> Hi All, >> I'm writing a backend for a target which only supports 4-byte, >> 4-byte-aligned loads and stores. I custom-lower all {*EXT}LOAD and >> STORE nodes in TargetISelLowering.cpp to take advantage of

On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson <johnso87 at crhc.illinois.edu> wrote: > Hi All, >     I'm writing a backend for a target which only supports 4-byte, > 4-byte-aligned loads and stores.  I custom-lower all {*EXT}LOAD and > STORE nodes in TargetISelLowering.cpp to take advantage of all alignment > information available to the backend, rather than treat each

On Wed, Jul 27, 2011 at 3:50 PM, Matt Johnson <johnso87 at crhc.illinois.edu> wrote: > Hi Eli, > > On 07/27/2011 04:59 PM, Eli Friedman wrote: >> >> On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson >> <johnso87 at crhc.illinois.edu>  wrote: >>> >>> Hi All, >>>     I'm writing a backend for a target which only supports 4-byte,

I"m getting build errors I think from one of your patches O tjoml. You need to have a build area that builds with clang and does warnings as errors to avoid these issues on putback. here is my configure step for example: /home/rkotler/llvm_trunk/configure --enable-werror --prefix=/home/rkotler/ll vm/install CC=/home/rkotler/llvm_3_2/install/bin/clang CXX=/home/rkotler/llvm_3_

It is r195843 and fixed in r195905, FYI. 2013/11/29 Reed Kotler <rkotler at mips.com>: > I"m getting build errors I think from one of your patches O tjoml. > > You need to have a build area that builds with clang and does warnings as > errors to avoid these issues on putback. > > here is my configure step for example: > /home/rkotler/llvm_trunk/configure

I'm still seeing this problem. On 11/28/2013 09:37 AM, NAKAMURA Takumi wrote: > It is r195843 and fixed in r195905, FYI. > > 2013/11/29 Reed Kotler <rkotler at mips.com>: >> I"m getting build errors I think from one of your patches O tjoml. >> >> You need to have a build area that builds with clang and does warnings as >> errors to avoid these

Hi, I am having issues running a new backend that I created for a new architecture. I suspect these errors may have something to do with how I have the string setup in LLVMTargetMachine() below? Also - It would be great if someone could point me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help

Hi all, I'm working with some data: 54 variables and a column of classes, each observation as one of a possible seven different classes: > var.can3<-lda(x=dados[,c(1:28,30:54)],grouping=dados[,55],CV=TRUE) Warning message: In lda.default(x, grouping, ...) : variables are collinear > summary(var.can3) Length Class Mode class 30000 factor numeric ### why?? I

Hi All, Some targets don't provide subword (e.g., i8 and i16 for a 32-bit machine) load and store instructions, so currently we have to custom-lower Load- and StoreSDNodes in our backends. For examples, see LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I believe it's possible to support this lowering in a target-agnostic fashion in LegalizeDAG.cpp, similar to

Hi, The ldN like intrinsics (including all the ld1xN, ldN, ldNlane, ldNr, stN, stNlane) can use any pointer types. The definition (in IntrinsicsAArch64.td) of such intrinsics use 'LLVMAnyPointerType', which means we can pass any pointer type to such intrinsics. E.g. I tried following case ld2.ll: define { <4 x i32>, <4 x i32> } @test(float* %ptr) { %vld2 = call {

On 16 Jul 2011, at 03:34, Matt Johnson wrote: > Hi All, > Some targets don't provide subword (e.g., i8 and i16 for a 32-bit > machine) load and store instructions, so currently we have to > custom-lower Load- and StoreSDNodes in our backends. For examples, see > LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I > believe it's possible to

Hi, while writing my register allocator, I have come across a case which confuses me because the llvm definition cannot be mapped to machine code. For instance I come across (1) and I reduce it to (2). However a copy instruction cannot move from EDX to CX. What mechanics in LLVM will tell me that I cannot make this move during register allocation, or how can I tell from (1) that I cannot execute

While migrating my codebase from llvm-2.6 to llvm-2.7, I found a different behaviour in the register allocation. I have been able to reproduce it using the msp430 backend, with the 2.7 release as well as the svn head. For the msp430, the first four parameters of a function are passed thru registers. What I observe is that if those parameters are not used inside the function, those registers can

Greetings, I'm investigating a bug in the PowerPC back end in which a load from a storage address is being reordered prior to a store to the same storage address. I'm quite new to LLVM, so I would appreciate some help understanding what I'm seeing from the dumps. I assume that some information is missing that would represent the memory dependency, but I don't know what form that

Here's another data point that may be useful. [Scheduling experts, please help! :) ] If the two-byte bitfield is replaced by a two-byte struct (replace "short i:8" with "short i", etc.), the scheduler properly generates a dependency between the store and the load. For this case, a GEP is used instead of a bitcast:

Hi Bill, Which scheduler do you use? MI or SDNode one? In either case the problem is likely the same, but cause might be in a different place... The way I see it, you have an issue with the alias analyzer, not scheduler. When scheduling DAG is constructed, AA is checked for pairs of mem accessing objects, and if no potential interference is flagged by the AA the chain edge is _not_ inserted.

On Fri, 2012-09-21 at 11:34 -0500, William J. Schmidt wrote: > Hi Sergei, > > Thanks for the response! We just discovered there is likely a bug > happening during post-RA list scheduling. There's an invalid successor > index in the scheduling graph that is probably supposed to be the > missing arc. Starting to investigate further now. This is recorded in >

Hi Sergei, Thanks for the response! We just discovered there is likely a bug happening during post-RA list scheduling. There's an invalid successor index in the scheduling graph that is probably supposed to be the missing arc. Starting to investigate further now. This is recorded in http://llvm.org/bugs/show_bug.cgi?id=13891. Thanks, Bill On Fri, 2012-09-21 at 11:15 -0500, Sergei Larin

On Nov 8, 2010, at 12:04 PM, Jeff Kunkel wrote: > Hi, while writing my register allocator, I have come across a case which confuses me because the llvm definition cannot be mapped to machine code. > > For instance I come across (1) and I reduce it to (2). However a copy instruction cannot move from EDX to CX. What mechanics in LLVM will tell me that I cannot make this move during

Hi, I have done different discriminant function analysis of multivariat data. With the CV=True option I was not able to perform the predict() call. What do I have to do? Or is there no possibility at all? You also need the predicted values to produce a plot of the analysis, as far as I know. Here my code: pcor.lda2<-lda(pcor~habarea+hcom+isol+flowcov+herbh+inclin+windprot+shrubcov+baregr,