similar to: [LLVMdev] Use of -mllvm -debug (clang)

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Use of -mllvm -debug (clang)"

2014 May 01
2
[LLVMdev] What is HexagonTargetMachine::addPassesForOptimizations for?
On 4/30/2014 5:24 PM, Craig Topper wrote: > Pranav, can you remove it? > Yes, I'll remove it. Pranav -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
2012 Nov 09
3
[LLVMdev] inttoptr and basicaa
Hi, I am observing some incorrect behavior in basicaa, wherein two pointers that basicaa should determine to be MustAlias are ending up NoAlias - the other extreme :( I am blaming this on basicaa not handling inttoptr. Here is the relevant IR snippet. -------------------- %sunkaddr36 = ptrtoint %struct.BitParams* %bs to i32 %sunkaddr37 = add i32 %sunkaddr36, 16 %sunkaddr38 = inttoptr i32
2012 Jul 05
3
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation
2014 Apr 30
2
[LLVMdev] What is HexagonTargetMachine::addPassesForOptimizations for?
On 4/30/2014 2:00 PM, Matthew Curtis wrote: > On 4/30/2014 9:01 AM, Krzysztof Parzyszek wrote: >> On 4/30/2014 8:45 AM, Rafael EspĂ­ndola wrote: >>> On 30 April 2014 00:52, Craig Topper <craig.topper at gmail.com> wrote: >>>> This function is marked virtual but doesn't override anything, >>>> doesn't have >>>> any overrides, and
2012 Aug 31
3
[LLVMdev] Question regarding ReplaceValueWith and ReplaceNodeResults
Hi, I am defining Hexagons version of ReplaceNodeResults to change the a node of the type A: i8 = INTRINSIC_WO_CHAIN ... , ... , To B: SIGN_EXTEND (A) After returning from my function, the type legalizer calss ReplaceValuesUsesWith to replace the uses of A with B. Unfortunately, it replaces the use of A in the new node B too. So the node now is B: SIGN_EXTEND(B) , which is clearly bad and the
2011 Jul 13
2
[LLVMdev] overflow check
Hi, I have three constants (B, C and V) and V = B + C. I want to find out if B + C wraps around. The way I'll do it is, assuming B and C are both positive, to check if V < B or C. For this I need the values of B, C and V. I tried using APInt as below. *** If (isa<Constant> (B) && isa<Constant> (C) && isa<Constant>(V)) { ConstantInt *CV =
2012 Jul 05
2
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi, This question relates to the undef flag in the context of sub-register def operands. 1) Firstly, the documentation (comments in the source code) says that in a sub-register def operand, the "IsUndef" flag refers to the part of the register that is not written. 2) Further, the documentation about readsReg() states that a sub-register def implicitly reads the other parts of the
2012 Mar 08
2
[LLVMdev] A question about DBG_VALUE and Frame Index
Hi, I have a case that is causing me grief in the form of an assert. The prolog Epilog inserter tries to remove Frame Index references. I have a DBG_VALUE instruction that looks like this (alongwith the Frame Index). This is for the Hexagon backend. ************************** fi#2: size=4, align=4, at location [SP-84] DBG_VALUE <fi#2>, 0, !"fooBar"; line no:299
2012 Jul 06
2
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
On Jul 5, 2012, at 6:01 PM, "Pranav Bhandarkar" <pranavb at codeaurora.org> wrote: > Hi Jakob, > >> New_MI_1:: Vreg1 = 0 ; Vreg1 and Vreg2 >> are 32 bit virt. regs. >> New_MI_2:: Vreg2 = COPY C:lo_sub_reg. >> New_MI_3:: B= REG_SEQUENCE<Vreg1, hi_sub_reg, Vreg2, lo_sub_reg> ; B >> is a >> 64 bit
2012 Jul 06
0
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi Jakob, > New_MI_1:: Vreg1 = 0 ; Vreg1 and Vreg2 > are 32 bit virt. regs. > New_MI_2:: Vreg2 = COPY C:lo_sub_reg. > New_MI_3:: B= REG_SEQUENCE<Vreg1, hi_sub_reg, Vreg2, lo_sub_reg> ; B > is a > 64 bit virt reg. I used this approach and it worked find until I hit, what I believe is, a bug in the register coalescer. When the register
2012 Sep 13
2
[LLVMdev] teaching FileCheck to handle variations in order
> Can you explain why you were unable to add a small unit test to the testsuite? This is the case I have. ****** r3 = memb(r1+#1) r4 = memb(r1+ #0) .. .. { p0 = r3 /* Should almost never emit this. */ p1 = r4 /* Should almost never emit this. */ .. .. p0 = or(p1, p0) ***** The CHECK tags I have are ; CHECK: [[IntReg0:r[0-9]+]]
2011 Jul 21
0
[LLVMdev] Use of -mllvm -debug (clang)
On 20 July 2011 20:24, Bhandarkar, Pranav <pranavb at quicinc.com> wrote: > I have been trying to use the -mllvm -debug option for clang but without much success. Do I need to build in any specific manner for this to work ? You need to build LLVM with assertions enabled.
2012 Oct 25
2
[LLVMdev] A question about pointer aliasing rules in LLVM
Hi, I have the following IR code </snippet> %prev = getelementptr inbounds %struct.myStruct* %node, i32 0, i32 1 %1 = load %struct.myStruct** %prev, align 4, !tbaa !0 %next1 = getelementptr inbounds %struct.myStruct* %1, i32 0, i32 0 store %struct.myStruct* %0, %struct.myStruct** %next1, align 4, !tbaa !0 %2 = load %struct.myStruct** %prev, align 4, !tbaa ! </snippet> myStruct is
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Pranav Bhandarkar > Sent: Thursday, April 26, 2012 5:24 PM > To: llvmdev at cs.uiuc.edu > Subject: [LLVMdev] MemRefs in a Load Instruction > > Hi, > > On the hexagon target, I have written a following combiner pattern. >
2012 Nov 09
0
[LLVMdev] inttoptr and basicaa
On Thu, Nov 8, 2012 at 6:53 PM, Pranav Bhandarkar <pranavb at codeaurora.org> wrote: > Hi, > > I am observing some incorrect behavior in basicaa, wherein two pointers that > basicaa should determine to be MustAlias are ending up NoAlias - the other > extreme :( > I am blaming this on basicaa not handling inttoptr. Here is the relevant IR > snippet. >
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
Hi, On the hexagon target, I have written a following combiner pattern. ********************************************* def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset1)))), (i32 32))), (i64 (zextloadi32 ADDRriS11_2:$src2)))), (i64 (COMBINE_rr
2012 Jul 06
0
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
> > > That sounds like a bug, probably adjustCopiesBackFrom needs to check > ACopyMI->isFullCopy(). > > Do you have a test case for this? > > Yes and No. Yes because the example is from a unit testcase that I have. No because it manifests itself only with my half baked pass that I was talking about earlier in this thread. Pranav -------------- next part --------------
2013 Jul 11
1
[LLVMdev] Scalar Evolution and Loop Trip Count.
Hi, Scalar evolution seems to be wrapping around the trip count in the following loop. void add (int *restrict a, int *restrict b, int *restrict c) { char i; for (i = 0; i < 255; i++) a[i] = b[i] + c[i]; } When I run scalar evolution on the bit code, I get a backedge-taken count which is obviously wrong. $> cat loop.ll ; Function Attrs: nounwind define void @add(i32* noalias
2011 Oct 25
1
[LLVMdev] Using a FunctionPass inside a CallGraphSCCPass
Hi, I am writing a CallGraphSCCPass that uses LoopInfo which is a FunctionPass. However, doing so results in the following error. **** Unable to schedule 'Natural Loop Information' required by '......' **** Google led me to this page, where Devang Patel suggests implementing the addLowerLevelRequiredPasses in CGPassManager in a manner similar to MPPassManager.
2012 Oct 17
0
[LLVMdev] DWARF 2/3 backwards compatibility?
> My GDB Testsuite runs have been failing more tests, and now an internal test > has started failing on some missing dwarf 3 records. What is the error message or the nature of the failures you are seeing ? Pranav Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation