similar to: [LLVMdev] [PATCH] Get DCE to consider livein PhysRegs to successor basic blocks.

Displaying 20 results from an estimated 8000 matches similar to: "[LLVMdev] [PATCH] Get DCE to consider livein PhysRegs to successor basic blocks."

2011 Jun 21
0
[LLVMdev] [PATCH] Get DCE to consider livein PhysRegs to successor basic blocks.
On Jun 21, 2011, at 12:51 AM, Sanjoy Das wrote: > Adds code to have DCE start off with a list of physical registers to be > live on entry to at least one successor basic block (as mentioned in the > FIXME comment). Looks good, but keep the comment (sans FIXME).
2012 Sep 07
0
[LLVMdev] FastRegAlloc (wrongly?) marking physregs as free
Hi all, I am using the fast register allocator on a partially allocated machine function. I have noticed reserved registers (i.e. liveins) are marked as free after first use (in usePhysReg(..) method). This seems an error to me as a livein might be still used later in the basic block. As I understand this should check for isKill() before marking it as free, but I see it even *sets* the kill
2010 May 01
1
[LLVMdev] How to change successor of a regular Basic block
Hi, I am working with regular dominator tree and not MachineDominatorTree. I wanted to modify the CFG structure and for that I need to change successor of a basic block. How can I do that? Or is there a way to cast a BasicBlock to MachineBasicBlock so that i can use functions addSucessor and removeSuccessor for the basic block. It will be great if someone can help. regards, Ambika
2012 Feb 15
0
[LLVMdev] [llvm-commits] [PATCH] MachineRegisterInfo: Don't emit the same livein copy more than once
Hi Tom, As far as I can tell EmitLiveInCopies is just there to handle physreg arguments and return values. Is there any reason for these to change late in your backend? - Lang. On Tue, Feb 14, 2012 at 7:22 AM, Tom Stellard <thomas.stellard at amd.com>wrote: > On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > > Hi Tom, > > > > I'm pretty sure this
2004 Apr 08
0
Some basic questions about accessing DFS/DCE shares with SAMBA 3.0
Hi Guys- We are a group involved in a project to move an application from Windows to AIX, and part of the application involves reading OSF DFS shares, and making the filesystem available to Windows machines through SAMBA. The conversion of the application has gone well, but it is our first time using SAMBA and I have some questions that hopefully are not too dumb, and if they are, we would gladly
2012 Feb 14
2
[LLVMdev] [llvm-commits] [PATCH] MachineRegisterInfo: Don't emit the same livein copy more than once
On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > Hi Tom, > > I'm pretty sure this function should only ever be called once, by > SelectionDAG. Do you know where the second call is coming from in your code? > > Cheers, > Lang. Hi Lang, I was calling EmitLiveInCopies() from one of my backend specific passes. If the function can only be called once, then
2011 Jan 06
1
[LLVMdev] Pass to compute livein info
Hi all, Is there a pass that computes livein information for each MachineBasicBlock? I tried to find such a pass but could not find any. I am trying to use the livein information to get dead registers to insert some instructions right before code emission but the livein information seems to be invalidated by some pass. I might need to recompute the livein information before my pass. Thanks a
2013 Jul 31
0
[LLVMdev] Maintaining LiveIn
I would like to maintain the livein information for physical registers on basic blocks past register allocation, or recreate it if possible. The goal is to be able to run a late pass of DeadMachineInstrElim, which requires valid livein information. The X86 target returns false for requiresRegisterScavenging so passes like BranchFolding don't update the livein information. At that point I
2012 Feb 14
0
[LLVMdev] [llvm-commits] [PATCH] MachineRegisterInfo: Don't emit the same livein copy more than once
Hi Tom, I'm pretty sure this function should only ever be called once, by SelectionDAG. Do you know where the second call is coming from in your code? Cheers, Lang. On Mon, Feb 13, 2012 at 7:03 PM, Stellard, Thomas <Tom.Stellard at amd.com>wrote: > This patch seems to have been lost on the llvm-commits mailing list. > Would someone be able to review it? > > Thanks, >
2012 Feb 14
2
[LLVMdev] [llvm-commits] [PATCH] MachineRegisterInfo: Don't emit the same livein copy more than once
This patch seems to have been lost on the llvm-commits mailing list. Would someone be able to review it? Thanks, Tom ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] on behalf of Tom Stellard [thomas.stellard at amd.com] Sent: Friday, February 03, 2012 1:55 PM To: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits]
2008 Jan 10
5
Extracting last time value
I have a dataframe as follows: Date time value 20110620 11:18:00 7 20110620 11:39:00 9 20110621 11:41:00 8 20110621 11:40:00 6 20110622 14:05:00 8 20110622 14:06:00 6 For every date, I want to extract the row that has the greatest time. Therefore, ending up like: 20110620 11:39:00 9 20110621 11:41:00 8 20110622 14:07:00 6 I am using for loops (for every date, find largest time value) to do
2016 Jan 30
0
DCE in the presence of control flow.
In practice, APT is not faster to build than rdf. The df calculator we use is linear time and quite fast. Updating is also pretty trivial since it's only deletes of dead and unreachable code. So anything it reached can be replaced with undef in most cases. Cd-dce is not slower in GCC than dce On Fri, Jan 29, 2016, 8:31 PM David Callahan <dcallahan at fb.com> wrote: > I think you
2016 Jan 29
3
DCE in the presence of control flow.
On Thu, Jan 28, 2016 at 10:09 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"David Callahan via llvm-dev" <llvm-dev at lists.llvm.org> > *To: *"Daniel Berlin" <dberlin at dberlin.org>, "LLVM Dev Mailing list" < > llvm-dev at lists.llvm.org> > *Sent: *Thursday, January 28, 2016
2016 Aug 23
2
Help in understanding physreg LiveVariables
<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" > </div> <div dir="ltr" >Hi all,</div> <div dir="ltr" > </div> <div
2016 Jan 30
0
DCE in the presence of control flow.
Maybe I was too quick here. Does gcc record the incoming edge to a phi? If so, won’t those change when you delete blocks in a non-trivial manner? How are those updated? From: David Callahan <dcallahan at fb.com<mailto:dcallahan at fb.com>> Date: Saturday, January 30, 2016 at 7:02 AM To: Daniel Berlin <dberlin at dberlin.org<mailto:dberlin at dberlin.org>>, Hal Finkel
2011 Aug 02
0
[LLVMdev] Multiple successors, single dynamic successor
I'm assuming that you're talking about a situation where this can't be determined statically in the existing LLVM IR, but you know it's true and want to put it in (e.g. you're the one generating LLVM IR). If that's not the case, then see if JumpThreading will do it for you. I'm not familiar with a way to express exactly what you want to say, but are you opposed to just
2011 Aug 02
2
[LLVMdev] Multiple successors, single dynamic successor
Suppose I have a bb with N predecessors and N successors. What is, in your opinion, the best way to express that the bb has (dynamically) only one successor (i.e. if coming from the i-th predecessor we will always jump to the i-th successor)? b.r., -- Carlo Alberto Ferraris <cafxx at strayorange.com <mailto:cafxx at strayorange.com>> website/blog
2016 Jan 30
3
DCE in the presence of control flow.
I had assumed you would treat phi nodes differently from other operations in that they don’t need to keep the block alive just to retain the data flow facts but it would be simplest to do that. Thanks Daniel From: Daniel Berlin <dberlin at dberlin.org<mailto:dberlin at dberlin.org>> Date: Friday, January 29, 2016 at 10:26 PM To: David Callahan <dcallahan at
2016 Aug 23
2
Help in understanding physreg LiveVariables
<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" >Matthias,</div> <div dir="ltr" > </div> <div dir="ltr" >Thanks for the response.</div> <div
2016 Jan 30
4
DCE in the presence of control flow.
I think you can also avoid the RDF computation using a more directed form of control dependence testing such as described in Keshav Pingali and Gianfranco Bilardi. 1997. Optimal control dependence computation and the Roman chariots problem. ACM Trans. Program. Lang. Syst. 19, 3 (May 1997), 462-491. DOI=http://dx.doi.org/10.1145/256167.256217 However one challenge seems to be fixing the SSA graph