similar to: [LLVMdev] arm processor support by llvm

Hi, I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. Here is output: # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) Target: arm-unknown-freebsd Thread

On 22 June 2011 11:49, Damjan Marion <damjan.marion at gmail.com> wrote: > # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c Even though you specified cpu as arm9, it's probably generating generic ARM IR (use -emit-llvm -S and see), which defaults to ARM instructions. If you want thumb, use triple =

On Jun 22, 2011, at 3:16 PM, Renato Golin wrote: > On 22 June 2011 11:49, Damjan Marion <damjan.marion at gmail.com> wrote: >> # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c > > Even though you specified cpu as arm9, it's probably generating > generic ARM IR (use -emit-llvm -S and see), which defaults

Good day, I have looked around for this information, but I have not been able to gain a clear understanding: what is the status of the LLVM ARM backend? That is, do the following work: 1. Generating Thumb code: I saw a video online where they describe an issue with using the ARM Thumb back-end 2. Generating code for ARM9 (ARMv5?) or ARM7 (ARMv4): again, the same presentation

Evan, > I'm the code owner of LLVM codegen and targets. I'm also the one of main developers on the original ARM target. That means, I would make the decisions on major development on ARM target if there are decisions to be made. > > But my role is very different from what people are looking for in this thread. To properly qualify a target like ARM which are supported on many

I have a question regarding ARM support. It was mentioned in mails below that LLVM supports ARM v6 but a lot of ARM v6 instructions are actually missing from ARM ISA description files( e.g. Media Instructions). Is there any documentation mentioning the unsupported parts of v6 version Thanks --Kapil On Thu, Sep 18, 2008 at 2:14 PM, Evan Cheng <evan.cheng at apple.com> wrote: > > On

On Sep 17, 2008, at 3:00 PM, Tyler Wilson wrote: > Good day, > > I have looked around for this information, but I have not been able > to gain a clear understanding: what is the status of the LLVM ARM > backend? That is, do the following work: > > 1. Generating Thumb code: I saw a video online where they > describe an issue with using the ARM Thumb back-end

Can you give some examples of missing instructions? Evan On Oct 9, 2008, at 4:58 PM, kapil anand wrote: > I have a question regarding ARM support. It was mentioned in mails > below that LLVM supports ARM v6 but a lot of ARM v6 instructions are > actually missing from ARM ISA description files( e.g. Media > Instructions). Is there any documentation mentioning the unsupported

Media instructions like - parallel add and subtract, Sign/Zero Extend and Add instructions seem to be missing from ARM target support. These instructions are not listed in GenInstrNames.inc Kapil On Fri, Oct 10, 2008 at 11:54 AM, Evan Cheng <evan.cheng at apple.com> wrote: > > Can you give some examples of missing instructions? > > Evan > > On Oct 9, 2008, at 4:58 PM,

Hi > I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. > > Here is output: > > # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c > clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) >

Hi, > I am using a cross compiler to compiler for the arm5 architecture. For this > architecture it is not allowed that a destination register is also used as source > register. > In 2007 a patch was discussed at the mailing list, however my compiler still is > producing this result. Does anyone know if this patch is actually applied? > > * I use the following arguments:

ACE issued following PR: http://www.ace.nl/news/aces-cosy-compiler-framework-outperforms-llvm-arm9-processor Weird that they don't give any number and use ARM 9, do they mean cortex-a9 ?

Hi, I am using a cross compiler to compiler for the arm5 architecture. For this architecture it is not allowed that a destination register is also used as source register. In 2007 a patch was discussed at the mailing list, however my compiler still is producing this result. Does anyone know if this patch is actually applied? * I use the following arguments: llvm-gcc -mfpu=vfp -mlittle-endian

Hi all, I'm trying to use libspeex 1.1.10 on an ARM926EJ-Sid(wb) rev 3 (v5l). I executed the speexenc and speexdec test files and they can encode and decode. But I'm getting 95% of cpu utilization on the codification and 44% on the decodification. I saw in the post: http://lists.xiph.org/pipermail/speex-dev/2005-June/003485.html that this version of speex works fine on ARM

Hi, I tried the same options suggested in your post and the problem continues. What do you suggest? 2005/9/15, Jean-Marc Valin <Jean-Marc.Valin@usherbrooke.ca>: > Hi Eduardo, > > All I can say is that the timings you have are a bit odd. What > optimizations options are you using (I suggest -O3)? Also, perhaps you > can try --enable-arm4-asm just in case. I've had the

On 26 February 2013 16:14, David Blaikie <dblaikie at gmail.com> wrote: > I'm not sure I understand your question. Fail tests continue to run so we > find out if they start passing as seems to be the case here. If llvm is now > free of whatever bugs caused these things to fail (ie: it's not just that > these stopped failing on this hardware but in all environments the

This is a note to announce the availability of "Ogg Theorarm", an optimised ARM implementation of decoding libraries for the Theora video code, and Vorbis audio codec from xiph.org. Full details of this code release can be found at <http://www.wss.co.uk/pinknoise/theorarm>, but highlights include: * Full speed playback of a 320x240x25fps clip with a 48kHz stereo audio track on

On Mon, 18 Sep 2006, [UTF-8] Rafael Esp?ndola wrote: >> "The destination register shall not be the same as the operand >> register Rm. R15 shall not be used as an operand or as the >> destination register." > > The ARM ARM has this "Operand restriction" on MUL: > Specifying the same register for <Rd> and <Rm> has UNPEDICTABLE

Hello, Nathan >   I may need to clarify, sparcv9-* is used for the SPARCV9 ABI (ie 64-bit ABI), rather than the SPARCV9 CPU per se. It serves the same purpose as x86_64-* and powerpc64-*, which is to say it's associated with -m64, not -mcpu=v9 (although unsurprisingly -m64 does require a V9 or later CPU). I may be wrong, but I think the only distinction in ARM is between arm and thumb

Hello, I wanted to know about the reasons Apple dropped the support for "arm" target in its ld64. After searching in the sourcecode I found out that ld64 supports armv4 armv5 armv6 armv7 and its subtypes. The code shows that -force_cpusubtype_ALL for ARM targets is no more supported in "src/ld/options.cpp") and static const ARMSubType ARMSubTypes[] doesn't include