similar to: [LLVMdev] X86Subtarget.h could be beautified

The current rule is: /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls /// to immediate address. bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const { if (In64BitMode) return false; return isTargetELF() || TM.getRelocationModel() == Reloc::Static; } But this is not doing the correct thing for ELF PIC. The straight-forward way to fix

Attached is a working patch set for llvm to be able to emit arm64 (currently as triple aarch64-apple-ios) mach-o object files, in case someone is interested. I'm not sure if the llvm maintainers want the patch given the previous message that there's going to be an official patch set from apple to support this, but here is mine. What works (tested on an iPhone 5S): * objc strings,

Does this fix it? Index: lib/Target/X86/X86Subtarget.h =================================================================== --- lib/Target/X86/X86Subtarget.h (revision 48879) +++ lib/Target/X86/X86Subtarget.h (working copy) @@ -144,9 +144,12 @@ std::string getDataLayout() const { const char *p; - if (is64Bit()) - p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128"; -

Probably better to move the discussion to a bug? Evan On Mar 27, 2008, at 9:04 AM, Duncan Sands wrote: > Does this fix it? > > Index: lib/Target/X86/X86Subtarget.h > =================================================================== > --- lib/Target/X86/X86Subtarget.h (revision 48879) > +++ lib/Target/X86/X86Subtarget.h (working copy) > @@ -144,9 +144,12 @@ > >

On Monday 30 March 2009 16:12, David Greene wrote: > There is some redundancy at the instruction format level in the x86 .td > files. For example, in X86InstrFormats.td: > > // SSE1 Instruction Templates: > // > // SSI - SSE1 instructions with XS prefix. > > class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> > pattern> > >

Hi all, I think I found a bug in LLVM 3.0: When compiling for a target without SSE2 support, there were some 128-bit PXOR instructions in the generated code. I traced it down to the following definition in X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>,

On Fri, Jan 20, 2012 at 2:47 PM, Nicolas Capens <nicolas.capens at gmail.com> wrote: > Hi all, > > I think I found a bug in LLVM 3.0: When compiling for a target without > SSE2 support, there were some 128-bit PXOR instructions in the generated > code. > > I traced it down to the following definition in X86InstrSSE.td: > >   def FsFLD0SS : I<0xEF, MRMInitReg,

There is some redundancy at the instruction format level in the x86 .td files. For example, in X86InstrFormats.td: // SSE1 Instruction Templates: // // SSI - SSE1 instructions with XS prefix. class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; // SSE3 Instruction

On Mar 30, 2009, at 2:53 PM, David Greene wrote: > On Monday 30 March 2009 16:12, David Greene wrote: >> There is some redundancy at the instruction format level in the >> x86 .td >> files. For example, in X86InstrFormats.td: >> >> // SSE1 Instruction Templates: >> // >> // SSI - SSE1 instructions with XS prefix. >> >> class

> How can having an MSVC compatible compiler be to the detriment of clang and > llvm? No one is trying to break mingw here, merely add support for something Just to make stuff clear: I just wanted proper naming which will be non-confusing. Right now we have: - isTargetWindows() which really means "msvc-compabile" - isTargetWin32() which means "everything on windows", so

2013/3/28 Anton Korobeynikov <asl at math.spbu.ru>: >> How can having an MSVC compatible compiler be to the detriment of clang and >> llvm? No one is trying to break mingw here, merely add support for something > Just to make stuff clear: I just wanted proper naming which will be > non-confusing. Right now we have: > - isTargetWindows() which really means

Hello, I am currently facing an issue at linking stage when compiling basic C code for an embedded PPC32 platform and linking with LLD. For external symbol linkage LLVM appears to use PLT which results in generating a R_PPC_PLTREL24 relocation, that is not support by LDD. Therefore even such a basic example cannot be built: /* s.c */ int f() { return 0; } /* t.c */ int f(); int _start() {

Rafael, I believe MachO can't represent this relocation, even in non-PIC mode. On my Mac, I tried compiling "call 256". I got: in section __TEXT,__text reloc 0: R_ABS reloc but no absolute symbol at target address I believe the correct thing to do is: isTargetELF() && TM.getRelocationModel() == Reloc::Static This will do the right thing on ELF, and the right thing on

On Jun 6, 2008, at 11:55 AM, Dan Gohman wrote: > On Fri, 2008-06-06 at 17:08 +0100, Rafael Espindola wrote: >> 2008/6/6 Anton Korobeynikov <asl at math.spbu.ru>: >>> Hello, Rafael >>> >>> Awesome! But... -ENOPATCH :( >> >> Attached now. > > Hi Rafael, > > Thanks a lot for working on this! > > I have one question about the

It seems that the || should be && here? /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls /// to immediate address. bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const { if (Is64Bit) return false; return isTargetELF() || TM.getRelocationModel() == Reloc::Static; } For example, if you are doing ELF PIC (i.e. for a shared

> And this command: > > $ llc -mtriple "i686-linux-gnu" test.ll -o test.s -filetype=asm > -relocation-model=pic I can reproduce it now. Sorry, I was using a test returning void and we don't have tail call of immediate. My impression in that the right fix would be to just remove the "isTargetELF()". It would make the function correct for ELF and not less

2011/10/21 David Meyer <pdox at google.com>> Rafael, > > I believe MachO can't represent this relocation, even in non-PIC mode. > On my Mac, I tried compiling "call 256". I got: I think PIC is just the default (the kernel being non-PIC for example), but I am not sure. > in section __TEXT,__text reloc 0: R_ABS reloc but no absolute symbol > at target address

On Tuesday 31 March 2009 13:53, Dan Gohman wrote: > > class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, > > list<dag> pattern> > > > > : SSIb<o, F, outs, ins, asm, pattern>, Requires<HasSSE1>; > > Is this just factoring out the ", XS" part? As presented, it looks like > this change would introduce more

Can someone explain the magic behind the Pat<> construct and tblgen. >From X86InstrSSE.td: def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)), (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>; Where's the code in tblgen to emit the matching code for this? I'm trying to extend it so that Pat<> can be used as a

Hi, I noticed a bunch of psuedo instructions used for creation of constants without generating loads. e.g. pxor xmm0, xmm0 Here is an example of what i am referring to snipped from X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; My question is