similar to: [LLVMdev] Post-RA scheduler and IssueWidth

Hi Andrew, Thank you for explaining the situation. I also do understand that introducing "pseudo" resource locked by all instructions will fix the problem for 1-issue pipeline, but see it as a bit limiting for me at the moment. Anyway, the patch is attached. BR  m On Fri, May 27, 2011 at 1:54 PM, Andrew Trick <atrick at apple.com> wrote: > On May 26, 2011, at 7:29 PM, Max

Akira, Thanks you for response. I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But I found mips codes are good enough by default. basically, I can not easily eyeball any bubbles. I don't understand how they can do that without post-RA-sched. pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little information and they can only schedule node in topology

Hi, LLVM, I found LLVM codegen has 3 passes for instruction scheduling: 1) pre-ra sched 2) post-ra sched 3) mi sched. for RISC machines, there are data hazard cases appear only after Register Allocation(RA). for example, $t0 is used immediately after writing(RAW): ld $t0, MEM add $t2, $t0, $0 There may be one or more stall in pipeline. Instruction scheduler can detect this kinds of conflict

On Tue, 2011-11-22 at 13:27 -0600, Hal Finkel wrote: > On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote: > > On Oct 25, 2011, at 6:01 PM, Hal Finkel wrote: > > > Is there documentation somewhere for the bottom-up scheduling? I'm > > > trying to figure out what changes are necessary in order to support it > > > in the PPC backend. > > > >

Hello. I am new to the schedulers implemented in the back end of LLVM. I am trying to handle data hazards in my simple processor, with instructions that execute in 1 cycle. I have tried the standard post-RA scheduler, implemented in lib/CodeGen/PostRASchedulerList.cpp, (with a ScoreboardHazardRecognizer), but I have some issues with some consecutive instructions that are

Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you will have to compile with -O3. You can also invoke the MI (pre-RA) scheduler with llc option "-enable-misched". As you have pointed out, the post-isel scheduler is mandatory, and therefore you don't have to give any command line options. Currently, mips has only one generic scheduling itinerary model in

On Nov 29, 2011, at 10:47 AM, Hal Finkel wrote: > Andy, > > I should have been more clear, the ARM implementation has: > void ARMHazardRecognizer::RecedeCycle() { > llvm_unreachable("reverse ARM hazard checking unsupported"); > } > > How does that work? > > Thanks again, > Hal Hal, My first answer was off the top of my head, so missed the subtle

On Mon, 2011-11-28 at 15:45 -0800, Andrew Trick wrote: > > On Nov 28, 2011, at 3:35 PM, Hal Finkel wrote: > > > > > > > Is EmitInstruction used in bottom-up scheduling at all? The > > > version in > > > the ARM recognizer seems essential, but in all of the regression > > > tests > > > (and some other .ll files I have lying around),

On Nov 28, 2011, at 3:35 PM, Hal Finkel wrote: >> >> Is EmitInstruction used in bottom-up scheduling at all? The version in >> the ARM recognizer seems essential, but in all of the regression tests >> (and some other .ll files I have lying around), it is never called. It >> seems that only Reset() and getHazardType() are called. Could you please >> explain the

Hi, Akira, I found you maintain mips MipsSchedule.td. does it correct? in MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no ByPass info out there. are you sure this reflects the real R4xxx/R5xxx processors. why IILoad uses funcition unit ALU? InstrItinData<IILoad , [InstrStage<3, [ALU]>]> for my previous question, I have new input after

Andy, I should have been more clear, the ARM implementation has: void ARMHazardRecognizer::RecedeCycle() { llvm_unreachable("reverse ARM hazard checking unsupported"); } How does that work? Thanks again, Hal On Tue, 2011-11-29 at 09:47 -0800, Andrew Trick wrote: > ARM can reuse all the default scoreboard hazard recognizer logic such as recede cycle (naturally since its the

Is there documentation somewhere for the bottom-up scheduling? I'm trying to figure out what changes are necessary in order to support it in the PPC backend. Thanks in advance, Hal On Thu, 2011-10-20 at 10:21 -0700, Evan Cheng wrote: > > On Oct 19, 2011, at 7:29 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > > Evan, > > > > Thanks for the heads up! Is

On Oct 25, 2011, at 6:01 PM, Hal Finkel wrote: > Is there documentation somewhere for the bottom-up scheduling? I'm > trying to figure out what changes are necessary in order to support it > in the PPC backend. > > Thanks in advance, > Hal > > On Thu, 2011-10-20 at 10:21 -0700, Evan Cheng wrote: >> >> On Oct 19, 2011, at 7:29 PM, Hal Finkel <hfinkel at

ARM can reuse all the default scoreboard hazard recognizer logic such as recede cycle (naturally since its the primary client). If you can do the same with PPC that's great. Andy On Nov 29, 2011, at 8:51 AM, Hal Finkel <hfinkel at anl.gov> wrote: >> Thanks! Since I have to change PPCHazardRecognizer for bottom-up support >> anyway, is there any reason not to have it

On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote: > On Oct 25, 2011, at 6:01 PM, Hal Finkel wrote: > > Is there documentation somewhere for the bottom-up scheduling? I'm > > trying to figure out what changes are necessary in order to support it > > in the PPC backend. > > > > Thanks in advance, > > Hal > > > > On Thu, 2011-10-20 at

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the

Hello. I am progressing a bit with difficulty with the post RA scheduler (PostRASchedulerList.cpp with ScoreboardHazardRecognizer) - the problem I have is that it doesn't advance at the next available instruction when the overridden ScoreboardHazardRecognizer::getHazardType() method returns NoopHazard and it gets stuck at the same instruction (store in my runs). Just to make sure:

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

Hi, >From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in