similar to: [LLVMdev] Sources on optimization and debugging

Hi -- I'm still very much a newbie with llvm, but am looking (hopefully) to use it to compile into native intel code a set of source that is a combination of byte codes for my own custom vm and intel code that has been coded in assembly language directly. In an earlier exchange, I already discovered that llvm does not do any optimizations on intel assembly language code. This would be an

Hi Folks -- Let me go ahead and pose a question similar to the one Joachim poses below. I too am trying to evaluate whether LLVM will be of use to me in building a compiler and garbage collection mechanism for a byte code vm that I have built. Although there are multiple types of code that can be created with this system, all of them eventually translate to execution of one or more of these

Michael Clagett <mclagett at hotmail.com> writes: > There's about 32 core op codes that constitute the basic instruction > set and I can envision mapping each of these to some sequence of LLVM > IR. There's also a whole lot more "extended opcodes" that are > executed by the same core instruction execution loop but which are > coded using the built-in Intel

If you x86 assembly is sufficiently simple, I don't see any reason why you couldn't programmatically raise it back up to LLVM IR. People have tried this in the past (qemu, I think? I can't remember), and it usually results in some considerable slowdowns. I'd imagine that if your asm is sufficiently restricted, such as not needing to worry about arithmetic flags, the x87 FPU

Curious as to whether any work is in progress on this? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20101202/0ae5d181/attachment.html>

Sorry for the noise, but this is the message I meant to send to the list rather than replying to David directly. Unfortunately, I just sent his message to me before. From: mclagett at hotmail.com To: greened at obbligato.org Subject: RE: [LLVMdev] LLVM IR is a compiler IR Date: Thu, 6 Oct 2011 19:44:11 +0000 Thanks for your prompt reply. My answers are below at the end of your message.

Hi -- I'm wondering if some of you old hands might offer me some guidance. I've been working for some time with a virtual machine platform that is based loosely on the instruction set of a Forth hardware processor that Charles Moore designed sometime back. He used what he called a "MISC" or "Minimal Instruction Set Computer" and the original instruction set I was

On 9/13/11 9:22 AM, Michael Clagett wrote: > Oooohhh! That's interesting. Does the optimizer just work around > these inline fragments? Is there documentation for this facility? CC'ing the mailing list. The inline assembly feature is described in the LLVM Language Reference Manual (http://llvm.org/docs/LangRef.html). I'm not really familiar with what the LLVM optimizers

On 6/8/2015 5:08 PM, g wrote: > ie, partition for boot, partition for swap, partition for /, partition > home, partition for usr, partition for var, partition for home2, > partition for what ever. that model is not generally recommended anymore, at least not putting /usr on its own partition, there's just too many issues with that nowdays. I don't like putting /var in its

Hi. I'm trying to plot a pair of intertwined spirals and an svm that separates them. I'm having some trouble. Here's what I tried. > library(mlbench) > library(e1071) Loading required package: class > raw <- mlbench.spirals(200,2) > spiral <- data.frame(class=as.factor(raw$classes), x=raw$x[,1], y=raw$x[,2]) > m <- svm(class~., data=spiral) > plot(m,

I know the recommendation it to not run more than 2 T/E100P's in a system but what about X100P's.. Usually there are 5 PCI slots in a system, has anyone tried 5 x X100P's in a system? Later.. -- ______________________________________________ http://www.linuxmail.org/ Now with e-mail forwarding for only US$5.95/yr Powered by Outblaze

Hi All! I have the question, why reverted the ICH10 support from 7.1? This is the svn commit: http://svnweb.freebsd.org/viewvc/base/releng/?pathrev=186551 What is the PR number of the base of this commit or what is the problem description? I have a motherboard with ich10r with 3 sata2 disc (hitachi) + 1 sata dvd-rw (samsung), without any problem. Sorry for bad spelling or english

Hi all, I have a midsize AD domain with some 50k users but only 100 workstations joined. Sometimes I find server CPU throttling at 100%. In order to let it drop and have smooth performance I delete cache: systemctl stop samba net cache flush systemctl start samba First of all, is it needed a samba stop to flush the cache? Even if cache flush does the job to restore performance, I am clueless

On Jul 14, 2010, at 1:51 AM, Renato Golin wrote: > On 13 July 2010 17:54, Devang Patel <devang.patel at gmail.com> wrote: >> Yes. Thanks for catching this. >> Fixed r108246. > > Most welcome. ;) > > Btw, the 2.6 debug information (referred from the blog) doesn't warn > users that it's deprecated, nor it links to the new info (in an > obvious

On Wed, 2018-08-29 at 15:36 +0200, Peter Eriksson via samba wrote: > For what it’s worth you are not alone in seeing similar problems with Samba and gencache. > > Our site has some 110K users (university with staff & students (including former ones), and currently around 2000 active (SMB) clients connecting to 5 different Samba servers (around 400-500 clients per server). When we

On 13 July 2010 17:54, Devang Patel <devang.patel at gmail.com> wrote: > Yes. Thanks for catching this. > Fixed r108246. Most welcome. ;) Btw, the 2.6 debug information (referred from the blog) doesn't warn users that it's deprecated, nor it links to the new info (in an obvious manner, at least), that is completely different. That happens with the release notes that

Hi, from a generally pleased new rsync user. I have setup a number of services to be accessible via SSH. For most of them, it has been possible to arrange that clients can use a key agent and ssh's level 2 protocol to gain access without the need of entering passwords more than once, at the start of a session (assuming their keys are not stored in the clear). Most of these services can be

Hi, I coded some routines for YCbCr <-> RGB conversion, both using floating point numbers and using integer arithmetics, code is attached. Let's say I want to convert from RGB to YCbCr and back. First the integer arithmetics: In [1]: from colors import * In [2]: a = [255, 0, 255] In [3]: RGB2YCbCr(a) Out[3]: (107, 202, 222) In [4]: YCbCr2RGB(RGB2YCbCr(a)) Out[4]: array([255, 1,

LLVM and Clang both have lots of objects that are passed through many different API boundaries. Things like AliasAnalysis in LLVM or Sema in Clang get threaded all over the place. Over times, refactoring can often cause the parameters (or local variables, or member variables, etc) to become dead. If we notice this, we can often un-thread the interface through our APIs, sometimes even reducing

Is there are description somewhere of how CELT packs into the .oga file? Trying to reverse engineer it from the intertwined celtenc code is suboptimal. -a