similar to: [LLVMdev] TTA-Based Co-design Environment (TCE) v1.4 released

TTA-Based Codesign Environment (TCE) v1.3 released -------------------------------------------------- TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable codesign flow from C programs down to synthesizable VHDL and parallel program binaries. Processor

TTA-based Co-design Environment (TCE) is a toolset for design and programming of low power customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog generation supported) and parallel program binaries. Processor customization points

TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations,

TTA-based Co-design Environment (TCE) is a toolset for design and programming of low power customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog generation supported) and parallel program binaries. Processor customization points

Announcing the Release of TTA-Based Codesign Environment (TCE) v1.2 TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete codesign flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to

TTA-based Co-design Environment (TCE) v1.6 released --------------------------------------------------- TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and

2010/6/29 Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi>: > Hi, > > I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit > of a background for the TCE project in general. I hope some of you will find > it interesting :) > > http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html I'll ask here (rather than the TCE list)

Hi, I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit of a background for the TCE project in general. I hope some of you will find it interesting :) http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html -- Pekka

Hi all, I think this master's thesis from our group could be of interest. It describes the "bridge" between the LLVM codegen and our custom TTA codegen in TCE: a runtime retargetable architecture description file driven LLVM compiler backend. The thesis might be useful also for people implementing backends for LLVM in general. http://tce.cs.tut.fi/doc/Compiler.pdf If you have any

Hi, On 06/18/2011 06:26 AM, Benjamin Müller wrote: > i created a Function Pass to retrieve the Control/Data Flow Graph from > a simple program, > now i would like to statically schedule the Instructions. Is this > possible by starting to modify the SelectionDAG Files ? > Or can i even build a "standalone" custom scheduler? > Thank you very much for any tipps. You

Hello, Attached is a trivial patch to increase the max number of physical registers in LLVM from 1024 to 16384. In our TCE toolset we allow the designer to choose the number of registers in the designed TTA processors freely, and recently while experimenting with using TTA for a GPU design we have bumped into this limit several times. What has made matters a bit worse for us is that we need to

Hello LLVM people, Our customizable TTA target [1] is capable of having plenty of registers and register file ports to improve instruction level parallelism and reduce spills. It's totally up to the designer of the particular TTA processor how much the processor has registers and register file resources along with other TTA components. We have ported LLVM 2.1 to produce an intermediate TTA

On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote: > Hello LLVM people, > > Our customizable TTA target [1] is capable of having plenty of > registers > and register file ports to improve instruction level parallelism and > reduce spills. It's totally up to the designer of the particular TTA > processor how much the processor has registers and register file >

On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote: > Hello LLVM people, > > Our customizable TTA target [1] is capable of having plenty of > registers > and register file ports to improve instruction level parallelism and > reduce spills. It's totally up to the designer of the particular TTA > processor how much the processor has registers and register file >

Hi, Would it be possible to set tbgen to be installed with llvm? For our project http://llvm.org/ProjectsWithLLVM/#tta-tce it would be very helpful, because our tools generate compiler backend plugins in the fly for each customized processor and plugin generation needs tbgen for handling td files. Because of tbgen not beeing distributed, our users cannot use llvm from their favorite

Hello, Can someone please commit this patch? Thanks. On 11/21/2009 11:15 PM, Pekka Jääskeläinen wrote: > Hello, > > Attached is a trivial patch to increase the max number of physical > registers in LLVM from 1024 to 16384. > > In our TCE toolset we allow the designer to choose the number of > registers in the designed TTA processors freely, and recently > while

On 03.12.2013 14:30, Rafael Espíndola wrote: > Can you send a patch? Hi Rafael, the patch is attached. @Mikael, Tim Thanks for the help. I really needed only the link to the repo. Regards, Kai > > On 2 December 2013 06:44, Kai Nacke <kai at redstar.de> wrote: >> Hi! >> >> I like to submit some updates to the LLVM website regarding the LDC >> compiler. All

Hi Pekka, > Has anyone studied how much work it would be to implement an integrated > allocator/scheduler in LLVM now? Not to my knowledge. > Another solution (which we use in TCE) is to use register renaming. You do it in LLVM? Do you plan to upstream it? Also, I do not know your target/goal, but do you look at global scheduling at all? Thanks. Sergei -- Qualcomm Innovation