similar to: [LLVMdev] llvm vectorization position

Sounds like bundles will be the simplest to start with though I suppose I could just lower the pseudos after scheduling is done; for now. Bundles will prevent things from being able to be scheduled in more creative ways but for that I need to think more about the problem. So I can just create a bundle, insert instructions in it, and all will work more or less? I'm trying to take the next

AFAIK, You have two choices: use a pseudo that is lowered into separate instructions later as part of asm emission, or use MI bundles. The former is generally what existing targets use for this sort of thing, but perhaps the second would work better for you. Cameron On Feb 16, 2013, at 8:37 PM, Reed Kotler <rkotler at mips.com> wrote: > Some of my pseudos do conditional branch .+4 and

One of my reasons for lowering things early is that I need to get an accurate count of the size of things. Some of the pseudos even have instructions like compare immediate, which in Mips 16 has two forms depending on the magnitude of the immediate field. Though I suppose it's possible to leave things as a pseudo and calculate their size, though I'm not sure where I could store the

I see what my problem is here.... I'll continue to move further. Seems like Richards fix is still okay. On 02/25/2014 02:42 PM, Eric Christopher wrote: > On Tue, Feb 25, 2014 at 2:41 PM, reed kotler <rkotler at mips.com> wrote: >> On 02/25/2014 02:38 PM, Eric Christopher wrote: >>> On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote:

You are trying to do a few different things here, and a uniform solution may not work for all of them. For a fixed instruction sequence, e.g. a special kind of move-and-branch sequence used for tail calls, you probably want a pseudo. If you are trying to combine arbitrary instructions together, e.g. Thumb IT blocks, you probably want to use bundles, even if the sequences are a fixed length. I

I use the 'make TEST=simple' as a pre-commit test. I think that everybody should run these tests before committing to LLVM. On Dec 12, 2012, at 5:06 PM, reed kotler <rkotler at mips.com> wrote: > when I create the report, there are no failures in it. so maybe these are being filtered for known failures. > > On 12/12/2012 05:03 PM, reed kotler wrote: >> The first

On 02/25/2014 02:38 PM, Eric Christopher wrote: > On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote: >> On 02/25/2014 09:30 AM, Richard Sandiford wrote: >>> reed kotler <rkotler at mips.com> writes: >>>> On 02/24/2014 04:42 PM, Eric Christopher wrote: >>>>> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at

Hi Sean, Glad to hear there is clean up of tablegen going on. Just for the record, I don't know what you are referring to regarding some comment of mine at my talk about 10K LOC. I don't know how big tablegen is itself nor how much code has been written in it so I would not have ventured such a guess. The idea of totally replacing the tablegen language came up at the talk during the

----- Original Message ----- > From: "Reed Kotler" <rkotler at mips.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: LLVMdev at cs.uiuc.edu > Sent: Friday, November 22, 2013 11:18:53 PM > Subject: Re: bugpoint question > > In that case it tries to do something but fails. > > rkotler at ubuntu-rkotler:~/testmips16$ >

I definitely trust what you say now with time to think at your keyboard over what you said on the spot in a live presentation. The comment that I was referring to was: 36:44 of http://llvm.org/devmtg/2012-04-12/videos/Reed_Kotler-mobile.mov "there's not really more than a couple thousand lines of .td ... I mean there's not tons of this code so if we had to use a different one I

On 06/10/2014 05:51 PM, Pete Cooper wrote: > Hi Reed > > You can do this on the instruction itself by telling it 2 operands > must be the same register. For example, from X86: > > let Constraints = "$src1 = $dst" in > defm INSERTPS : SS41I_insertf32<0x21, "insertps">; > > Thanks, Hi Pete, Sorry. I should have been more specific. I'm

On 02/24/2014 04:42 PM, Eric Christopher wrote: > On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at mips.com> wrote: >> I need to leave soon and will take a look in the morning. >> >> I did look at the autoconf input files configure.ac >> >> There is a disable-zlib but not a disable-valgrind, even though it seems >> like there used to be.

On 02/25/2014 09:30 AM, Richard Sandiford wrote: > reed kotler <rkotler at mips.com> writes: >> On 02/24/2014 04:42 PM, Eric Christopher wrote: >>> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at mips.com> wrote: >>>> I need to leave soon and will take a look in the morning. >>>> >>>> I did look at the autoconf input files

That doesn't actually give you a guarantee that they won't be split up. Phases other than the scheduler may insert instructions in the middle of block (constant island pass, for example). Pseudo-instructions are the canonical answer to that problem. --Owen On Sep 17, 2013, at 11:09 PM, Micah Villmow <micah.villmow at smachines.com> wrote: > I used the A9 schedule as an

when I create the report, there are no failures in it. so maybe these are being filtered for known failures. On 12/12/2012 05:03 PM, reed kotler wrote: > The first one failed on a diff: > ******************** TEST (simple) 'sse.expandfft' FAILED! > ******************** > Execution Context Diff: > /home/rkotler/llvmpb3/build/projects/test-suite/tools/fpcmp: Compared: >

I used the A9 schedule as an example: http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td The documentation could use more clarity, but this is how I was able to do it to always get two specific instructions to be scheduled together. ________________________________________ From: reed kotler [rkotler at mips.com] Sent: Tuesday, September 17, 2013 8:54 PM To: Micah Villmow

Okay. Cool. So do you bootrstrap and verify as part of the usual testing? Do the nightly scripts do this? Reed On 06/28/2012 11:08 AM, Eric Christopher wrote: > On Jun 27, 2012, at 10:48 PM, Reed Kotler<rkotler at mips.com> wrote: > >> On 06/27/2012 05:00 PM, Eric Christopher wrote: >>> On Jun 19, 2012, at 5:24 PM, reed kotler<rkotler at mips.com> wrote:

On Tue, Jan 8, 2013 at 6:33 PM, reed kotler <rkotler at mips.com> wrote: > On 01/08/2013 01:48 PM, Eli Friedman wrote: >> >> On Mon, Jan 7, 2013 at 6:07 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> For example: >>> >>> /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel >>> -relocation-model=pic -o

//===----------------------------------------------------------------------===// // FalseParser //===----------------------------------------------------------------------===// class FalseParser : public parser<bool> { public: explicit FalseParser(Option &O) : parser<bool>(O) { } // parse - Return true on error. bool parse(cl::Option& O, StringRef ArgName, StringRef

On 09/17/2013 04:51 PM, Micah Villmow wrote: > Reed, > Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case. > > Micah > I'm not sure exactly what you mean. Can you point me to an example of that? TIA. Reed >>