similar to: [LLVMdev] sitofp inst selection in x86/AVX target [PR9473]

Displaying 20 results from an estimated 100 matches similar to: "[LLVMdev] sitofp inst selection in x86/AVX target [PR9473]"

2014 Oct 30
2
idmap weirdness - wildcard values being used instead of rfc2307 AD values
I've done a lot of research on this and haven't been able to solve the problem. Hopefully someone here has a better understanding of this than I do. The problem is that the UIDs and GIDs are not being fetched from AD. For example "getent passwd doug" returns: doug:*:70003:70005:Doug Meredith:/home/DSTRC/doug:/bin/false My full name has correctly been pulled from AD but the
2013 Oct 02
1
[LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction
Hi Jim, I did look at the ARMAsmParser and it seems to me that it is using a switch/case construct to change the opcode and the operands, but this construct may become too large eventually. I was wondering if it is possible to use isAsmParser only flag to call dedicated methods, like dedicated parsers for AsmOperands. Regards Vladimir ________________________________ From: Jim Grosbach [grosbach
2014 Mar 27
0
FreeBSD winbind UID/GID mapping weirdness
Quick summary: On FreeBSD 10, Winbind is giving me locally mapped UIDs & GIDS, rather than the ones specified in AD. I have two test member servers set up. A CentOS server running Sernet Samba 4.1.6 and a FreeBSD server running Samba 4.1.6 built from source. On CentOS, "getent group {group name}" gives me the correct GID assigned in AD. On FreeBSD I am given a value from the
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 24, 2015, at 4:46 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the snippet that matters: > > void > InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, > SDValue Op, > unsigned IIOpNum, > const MCInstrDesc *II, >
2013 Oct 02
0
[LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction
Hi Vladimir, ARM does similar things for complex assembly pseudos. Have a look at the definition and use of AsmPseudoInst in the ARM backend. They’re not typically expanding to multiple “real” instructions, but that’s an implementation detail, not a constraint. -Jim On Oct 1, 2013, at 5:36 AM, Vladimir Medic <Vladimir.Medic at imgtec.com> wrote: > Hi all, > I'm working on llvm
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Quentin, This is the issue. Somewhere prior to the constrainRegClass, it's assigning the GPRBase sub class of GPR to the MOV instruction, so it can't constrain it to Base and hence has to add the COPY. Now I just need to find out why it is ignoring the TableGen defined GPRBase for the MOV MI in favor of it's sub class GPR. Thanks. On Mon, Aug 24, 2015 at 8:34 PM, Ryan Taylor
2013 Oct 01
2
[LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction
Hi all, I'm working on llvm assembler support for Mips and for a while I'm trying to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Here is the instruction in question: multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass dstReg, ValueType srcAType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, [(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>; def IMM_REG :
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the multiclass. The IMM in my case is a global. So you can see that GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst operands, in this case (MOV16Copy_IMM_REG) it's the dst. 2. Yes I agree, it most likely would. Honestly, this comes across like a bug, or unintended feature. It's adding an extra COPY to
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
I have not tried 3.5, it's a significant amount of work to port from one version to the next though, I did not personally do the 3.4 to 3.6 porting. I agree though, it was very strange that it suddenly just changed behavior. It looks like to me that InstrEmitter.cpp:getVR is the one assigning the virtual register no? Though this code in CreateVirtualRegisters: const TargetRegisterClass *RC
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being generated. On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I have not tried 3.5, it's a significant amount of work to port from one > version to the next though, I did not
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
BB#0: derived from LLVM BB %entry %vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; GPRRegs:%vreg0 %vreg1<def> = COPY %vreg0; PTRRegs:%vreg1 GPRRegs:%vreg0 Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg1 RetRA This is what I get. This is what I'd like to get: BB#0: derived from LLVM BB %entry %vreg0<def> = MOV16Copy_IMM_REG
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I'm trying to do something like this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) > MRI->setRegClass(VReg, DstRC); >
2014 Dec 26
2
[LLVMdev] X86 disassembler & assembler mismatch
The IMM3/IMM5 come from here X86RecognizableInstr.cpp 943 TYPE("SSECC", TYPE_IMM3) 944: TYPE("AVXCC", TYPE_IMM5) On Thu, Dec 25, 2014 at 8:22 PM, Jun Koi <junkoi2004 at gmail.com> wrote: > > > On Fri, Dec 26, 2014 at 11:54 AM, Jun Koi <junkoi2004 at gmail.com> wrote: > >> hi, >> >> some instructions
2009 Apr 28
1
[LLVMdev] Register class intersection
When the coalescer is run with -join-cross-class-copies it needs to determine the register class of the joined virtual registers. The new register class must be compatible with both old register classes. The current implementation chooses the register class with the larger spill size, or the less populous class. This works with the current targets, but it can produce illegal machine code
2011 Sep 26
3
[LLVMdev] PTX backend do not support sitofp instruction?
Hi all, Does PTX backend support llvm sitofp instruction? I failed to compile my llvm source when use llc -march=ptx32. The reason is that the source has a sitofp instruction. After i changed the instruction into uitofp manually, it passed. Thanks in advance, best, Yabin -------------- next part -------------- An HTML attachment was scrubbed... URL:
2011 Sep 26
0
[LLVMdev] PTX backend do not support sitofp instruction?
> Does PTX backend support llvm sitofp instruction? Seems it doesn't support sitofp, search "Conversion to f32" in PTXInstrInfo.td. Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667
2011 Oct 21
2
[LLVMdev] convert integer to double "uitofp" or "sitofp" ?
Hello, As I understand, in LLVM IR it cannot be determined whether a register of type int is signed or unsigned. If one wants to convert an integer to a double, which instruction should be used:  "uitofp" or "sitofp" ? We track the values taken by all load instructions and we process them using a function. If the value is a pointer, we use int64 as the type of the function
2013 Jul 24
2
[LLVMdev] uitofp and sitofp rounding mode
When the uitofp and sitofp instructions convert e.g. from i64 to float, what rounding mode do they use? Answers in the form a patch to LangRef.html would be great! Thanks, Jay.