similar to: [LLVMdev] Calling convention

Have you added the $LLVM_INSTALL_DIR/bin to your PATH environment variable? Regarding changing a particular backend, check the documentation in http://llvm.org/docs/WritingAnLLVMBackend.html http://llvm.org/docs/CodeGenerator.html A few LLVMdev meetings have good talks to give you a good enough idea. http://llvm.org/devmtg/ Cheers, Raghu. ----- Original Message ----- From: "Teklu

Hi I am new to llvm and Linux (I am using ubuntu 10) My aim is to add backend to llvm. I install llvm using $ sudo apt-get install llvm and I am able to understand what I read about Writing an LLVM Compiler Backend. I have seen the assembly codes of the targets on llvm using llc. What I need now is to change some of the TableGen files of one of the target like SparcInstrInfo.td.  So I

On 06/29/12 11:12 PM, Renato Golin wrote: > On 29 June 2012 17:46, Karel Gardas<karel.gardas at centrum.cz> wrote: >> Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on >> ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The >> code in GHC is properly #ifdefed, so if there is no VFP available on pre >> ARMv6, then

David Terei wrote: > Hi all, > > I'm working on using LLVM as a back-end for the Haskell GHC compiler. As > part of that work I have modified LLVM to include a new custom calling > convention for performance reasons as outlined previously in a > conversation on this mailing list: > > http://nondot.org/sabre/LLVMNotes/GlobalRegisterVariables.txt > > This

Hi, I am mucking around with the pxelinux code for S&G's and I have a generic question about the pxe calling convention: Does the parameter structure and opcode HAVE to be passed onto the stack the PXE BIOS passed in when the pxelinux binary is executed at 0:7C00? The PXE spec says: "SS:SP is to contain the address of the beginning of the unused portion of the PXE services

> Message: 8 > Date: Tue, 27 Jan 2009 18:00:26 -0500 > From: "Jonathan S. Shapiro" <shap at eros-os.com> > Subject: Re: [LLVMdev] PPC calling convention -- how to provide an > environment pointer? > To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Message-ID: <1233097226.27873.11.camel at vmx> > Content-Type: text/plain > > On

On Tue, 2009-01-27 at 08:59 -0800, Stuart Hastings wrote: > I assume you're talking about the 32-bit PowerPC. Also 64-bit, but the two register usage conventions are very close. Someone previously pointed out that R0 is usable as a scratch register, and the CTR can be used. CTR *must* be used for the branch destination out of the ASM trampoline. R0 ends up getting used a lot for constant

Hi all, I'm working on using LLVM as a back-end for the Haskell GHC compiler. As part of that work I have modified LLVM to include a new custom calling convention for performance reasons as outlined previously in a conversation on this mailing list: http://nondot.org/sabre/LLVMNotes/GlobalRegisterVariables.txt This custom calling convention on x86-32 needs to handle just 4 parameters,

Hello, I'm working on implementing GHC specific call convention into LLVM 2.9. I've chosen LLVM 2.9 as a kind of stable reference point and I would like to know how mature is ARM code generation chain inside this release. I've had a hope that perhaps Apple as a main sponsor of LLVM is using LLVM for their ARM based iOS software development, but I'm not sure if I'm right

> Message: 5 > Date: Mon, 26 Jan 2009 21:47:12 -0500 > From: "Jonathan S. Shapiro" <shap at eros-os.com> > Subject: [LLVMdev] PPC calling convention -- how to provide an > environment pointer? > To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Message-ID: <1233024432.24380.11.camel at vmx> > Content-Type: text/plain > > This is

On 29 June 2012 17:46, Karel Gardas <karel.gardas at centrum.cz> wrote: > Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on > ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The > code in GHC is properly #ifdefed, so if there is no VFP available on pre > ARMv6, then it's not used. ie. GHC STG floating points regs are then >

This is not, strictly speaking, an LLVM issue, but it is an implementation matter that a compiler using LLVM needs to handle. I've got resolutions for other platforms, but I'm not seeing how to get this done for PowerPC, and I'ld appreciate suggestions or pointers. For BitC procedures that require an environment pointer, our general approach has been to construct a heap-allocated

Hi all I saw presentation http://www.softlab.ntua.gr/~gtsiour/files/erllvm_pres-20111107.pdf and I have couple question to the HiPE calling convention. I am trying to enable HiPE call for Rust compiler. That presentation mentioned that: Virtual registers with “special” use, pinned to hardware registers (unallocatable). VM Register AMD64 Register Native stack pointer %nsp Heap

Hi Renato, On 06/25/12 12:13 AM, Renato Golin wrote: > Hi Karel, > > I understand this patch has already been merged (to 3.0), so don't > take my question as stopping the merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9,

On 12 February 2010 14:01, Charles Davis <cdavis at mymail.mines.edu> wrote: > Something I'm doing right now may be of interest to you. > > Just today I added support for a new 'alignstack' function attribute. > With it, you can force the stack to be 16-byte aligned (or n-byte > aligned, if you so desire) in your functions. This way, you can make > calls to

On 04/24/12 17:10, Yiannis Tsiouris wrote: > This patch (and the others that will follow) are rebased on svn r155440: > > "AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8 > immediate. We can't use it here because the shuffle code does not check that > the lower part of the word is identical to the upper part" > > Patch 1/3: >

On Mar 26, 2008, at 1:31 PM, Óscar Fuentes wrote: > Óscar Fuentes <ofv at wanadoo.es> writes: > >> BTW, -fpcc-struct-return solves the case that motivated this thread. > > -fpcc-struct-return is an ABI change, hence it requires "compiling the > world". Not acceptable. > > I'll be interested on hearing ideas about how to determine how a > function

David, Thanks for that - I emailed Karel Gardas. I've got GHC successfully registerised on ARM, and I'm just starting on pushing it upstream. The reason why I'm avoiding the R0-R3 registers is mainly because my qemu-based ARM VM takes days to compile everything, and I was being conservative. The GHC code can call directly out to C, so it would need to save its own R0-R3 when it

Hi Kostis, Just to check, did you send the patch originally to llvmdev or llvm-commits? The latter is where all commit review takes place. Cheers, James -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Kostis Sagonas Sent: 02 May 2012 13:16 To: llvmdev at cs.uiuc.edu Cc: erllvm at softlab.ntua.gr Subject: Re: [LLVMdev] RFC:

Hi Karel, >>> > const unsigned* >>> > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) >>> const { >>> > + bool ghcCall = false; >>> > + >>> > + if (MF) { >>> > + const Function *F = MF->getFunction(); >>> > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);