similar to: [LLVMdev] Questions about LLVM IR encoding

Hi all, I am new to LLVM (even the field of compiler) and currently I am engaged in the work of adapting LLVM IR to M5 simulator to observe the enhancement of the novel architecture we design. Simply speaking if you know little about M5, my aim is to know how LLVM IR is interpreted and encoded, then try to implement it in the framework of M5. I have read the LLVM documents, yet I still have some

Peter Zotov писал 09.01.2013 19:59: > Hello. > > I've managed to create a bitcode file (attached; also available at > [1]) which produces > a series of identical errors when verified: > > | Global variable initializer type does not match global variable > type! > | %i.NilClass* @nil > > When ran through llvm-dis and recompiled, through, it verifies >

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set

I am currently working on DAGToDAGISel class for MIPS and am trying to figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return a value. My intrinsic is defined as: Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>; i.e. it has four arguments and one return value In DAGToDAGISel when I try to pass it with four arguments and

Hi all, I have a question with the "getelemptr" instruction. E.g.: I have some GEP instructions in my program. Some look like: <INST_GEP op0=26 op1=64 op2=429/> . <INST_GEP op0=341 op1=64 op2=101 op3=499 op4=0/> The first instruction above in assembly file: %tmp60 = getelementptr [512 x i32]* @weights, i32 0, i32 %k.3.ph Ok, we see it all: Index of @weights in value

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;

Hello. I've managed to create a bitcode file (attached; also available at [1]) which produces a series of identical errors when verified: | Global variable initializer type does not match global variable type! | %i.NilClass* @nil When ran through llvm-dis and recompiled, through, it verifies successfully. If I disassemble it one more time, the result is identical to the first

Hi, >> DAGCombiner::visitBRCOND() has code: >> >> SDValue N1 = N->getOperand(1); >> SDValue N2 = N->getOperand(2); >> >> ... >> >> SDNode *Trunc = 0; >> if (N1.getOpcode() == ISD::TRUNCATE&& N1.hasOneUse()) { >> // Look past truncate. >> Trunc = N1.getNode(); >> N1 = N1.getOperand(0);

Hi, Nick, thanks for the reply. I still have a problem: I only need to "clone" an Instruction, changing its type. That is, I would like to keep all characteristics of the old Instruction and create a new one only with a different type. I am trying create a new Instruction thus: %3 = add nsw i32 %1, %2 ; <i16> [#uses=2] //Old Instruction Value* Op0 = I->getOperand(0); Value*

I wrote in a few weeks ago about writing an independent implementation of Bitcode and updating the docs to be more complete. Attached is a patch to docs/BitCodeFormat.html that adds a lot of information that was previously only available by reading the source code. It also corrects some errors. Josh -------------- next part -------------- An HTML attachment was scrubbed... URL:

On 01/24/2011 04:41 AM, Douglas do Couto Teixeira wrote: > Hi, > > Nick, thanks for the reply. > I still have a problem: I only need to "clone" an Instruction, changing > its type. That is, I would like to keep all characteristics of the old > Instruction and create a new one only with a different type. Sure, but what about its operands? An "add" instruction

Dear All, The InstCombine pass performs the following transformation. Z / (X / Y) => (Y * Z) / X This is performed only when operand Op1 ( (X/Y) in this case) has only one use in future. The code snippet is shown below. if (match(Op1, m_OneUse(m_FDiv(m_Value(X), m_Value(Y)))) && (!isa<Constant>(Y) || !isa<Constant>(Op0))) { // Z / (X / Y) => (Y *

On Mon, Jan 24, 2011 at 3:01 PM, Nick Lewycky <nicholas at mxc.ca> wrote: > On 01/24/2011 04:41 AM, Douglas do Couto Teixeira wrote: > >> Hi, >> >> Nick, thanks for the reply. >> I still have a problem: I only need to "clone" an Instruction, changing >> its type. That is, I would like to keep all characteristics of the old >> Instruction

Our architecture has 1-bit boolean predicate registers. I've defined comparison def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; But then I end up having the following bug: Code %0 = zext i8 %data to i32 %1 = zext i16 %crc to i32 %2 = xor i32 %1, %0 %3 = and i32 %2, 1 %4 =

hi, i'm new in R and i need some help. Please, ¿do you know a function how can process cross tables for many variables and show the result in one table who look like this?: +----------------------------------------------------+ |------------------ | X variable | |----------------- | Xop1 | Xop2 | Xop3|.....| +----------------------------------------------------+ |Yvar1 |

On 1/24/11 12:05 PM, Douglas do Couto Teixeira wrote: > > > On Mon, Jan 24, 2011 at 3:01 PM, Nick Lewycky <nicholas at mxc.ca > <mailto:nicholas at mxc.ca>> wrote: > > On 01/24/2011 04:41 AM, Douglas do Couto Teixeira wrote: > > Hi, > > Nick, thanks for the reply. > I still have a problem: I only need to "clone" an

On 1 Oct 2010, at 13:35, Bill Wendling wrote: > On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > >> Bill Wendling wrote: >>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>> >>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>>

Hi, guys, Thanks a lot for your help. As you know, I am trying to implement something to change the types of the instructions. And I chose the trunc's approach because it seems be simple. But I still have some problems and questions. Would be great if you can help me. I have used the results of my range analysis implementation to change the intermediate representation. I am using