similar to: [LLVMdev] A small pass to constant fold branch conditions in destination blocks

Hi Jeff, > Are you sure this is really advantageous? '%c' is only one variable, but when > you add the constant propagation, '%c' and false/true are two different > variables. Thus the example was explanatory, not typical. In fact I didn't ever see returns being split like this in practice. What I do see typically is branches being eliminated. For example,

Are you sure this is really advantageous? '%c' is only one variable, but when you add the constant propagation, '%c' and false/true are two different variables. Thus define i1 @t1(i1 %c) { br i1 %c, label %t, label %f t: ret i1 %c f: ret i1 %c } should be br i1 R0, label %t, label %f t: ret R0 f: ret R0 However, with your pass define i1 @t1(i1 %c) { br i1

Then I misunderstood it's purpose. I see now that constant propagation could remove branches because you know a value is true. I was looking at the problem through my 'register allocator' lens. Here is a more expressive example of what you are doing. define i1 @t1(i1 %c) { br i1 %c, label %t, label %f t: br i1 %c, label %t2, label %f2 t2: code... ret something f2: code...

Duncan, GVN already does this. See lines 1669-1689. --Owen On Feb 7, 2011, at 4:50 AM, Duncan Sands wrote: > Hi all, I wrote a little pass (attached) which does the following: if it sees a > conditional branch instruction then it replaces all occurrences of the condition > in the true block with "true" and in the false block with "false". Well, OK, it > is a

Hi Jeff, sorry my example was misleading. > Then I misunderstood it's purpose. I see now that constant propagation could > remove branches because you know a value is true. I was looking at the problem > through my 'register allocator' lens. Here is a more expressive example of what > you are doing. > > define i1 @t1(i1 %c) { > br i1 %c, label %t, label %f

Here is a new and improved version that also does the following: if the condition for a conditional branch has the form "A && B" then A, B and the condition are all replaced with "true" in the true destination (similarly for || conditions in the false destination). Also, if the condition has the form "X == Y" then X is replaced by Y everywhere in the true

On Mon, Feb 7, 2011 at 8:54 PM, Duncan Sands <baldrick at free.fr> wrote: > Here is a new and improved version that also does the following: if the > condition for a conditional branch has the form "A && B" then A, B and the > condition are all replaced with "true" in the true destination (similarly > for || conditions in the false destination).  Also,

Duncan Sands wrote: > Here is a new and improved version that also does the following: if the > condition for a conditional branch has the form "A && B" then A, B and the > condition are all replaced with "true" in the true destination (similarly > for || conditions in the false destination). Also, if the condition has > the form "X == Y" then X

Nick Lewycky wrote: > Duncan Sands wrote: >> Here is a new and improved version that also does the following: if the >> condition for a conditional branch has the form "A && B" then A, B and the >> condition are all replaced with "true" in the true destination (similarly >> for || conditions in the false destination). Also, if the condition

On Feb 8, 2011, at 1:15 AM, Mark Shannon wrote: > Nick Lewycky wrote: >> Duncan Sands wrote: >>> Here is a new and improved version that also does the following: if the >>> condition for a conditional branch has the form "A && B" then A, B and the >>> condition are all replaced with "true" in the true destination (similarly

Hi, I'd like to understand how register allocation works in the case where an instruction is folded into another one. Where in the code would be a good place to start looking at? After ISEL, one of the instructions has another instruction folded into it, which looks like this t1: i32,i1,i1,i1,i1 = ADDRR TargetFrameIndex:i32<0>, MOVRI:i32,i1,i1 But during the 'Assembly

hi, Dear Evan Cheng: My cpu is i32 embeded CPU. I define pseudo register pair registers. In mytargetRegisterInfo.td: def T0: RegisterWithSubRegs<"t0",[R0,R1]>; ... def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] In mytargetISelLowering.cpp: I define i1, i8 , i16 and i32 are legal. 1. I still have problem. I save my function return double  value in

Hello all, How can I see the result of lazy value info analysis? I ran a command `opt -lazy-value-info -correlated-propagation -print-lazy-value-info example.ll -disable-output` with a following program as the input: ``` define i32 @f(i32 %a, i32 %b) { %i = icmp eq i32 %a, 10 br i1 %i, label %A, label %B A: %c = add i32 %a, 20 ret i32 %c B: ret i32 0 } ``` However, it shows a

(If this thread is becoming tiresome, let me know. This newbie is trying to understand some of what's going on; clearly you've thought about it way more than I have, and I can understand if you want to stop thinking about it!) On Mon, Dec 5, 2011 at 2:22 PM, Dan Gohman <gohman at apple.com> wrote: > On Dec 5, 2011, at 11:55 AM, Paul Robinson wrote: > > > > On Thu,

Hello R community, I am computing weighted average statistic by using ddply function: My data set is: N1 T1 S1 I1 C1 FY-4 ROE11 EPS11 MKT11 N1 T1 S1 I1 C1 FY-3 ROE12 EPS12 MKT12 N1 T1 S1 I1 C1 FY-2 ROE13 EPS13 MKT13 N1 T1 S1 I1 C1 FY-1 ROE14 EPS14 MKT14 N1 T1 S1 I1 C1 FY0 ROE15 EPS15 MKT15 N1 T1 S1 I1 C1 FY1 ROE16 EPS16 MKT16 N1 T1 S1 I1 C1 FY2 ROE17

On Nov 12, 2010, at 11:04 AM, Evan Cheng wrote: >> %z = select i1 %cond, i32 -1, i32 %x >> %s = and i32 %z, %y >> >> Is a "conditional and". It would be interesting to know if the ARM backend gets this as a single predicated 'and' instruction (similarly for the 'or' and 'xor' version of these patterns). I bet not, which is bad if

add -basicaa to your command line :) On Mon, May 11, 2015 at 7:15 AM, Willy WOLFF <willy.mh.wolff at gmail.com> wrote: > I play a bit more with MemoryDependenceAnalysis by wrapping my pass, and > call explicitely BasicAliasAnalysis. Its still using No Alias Analysis. > > How can I let MemoryDependenceAnalysis use BasicAliasAnalysis? > > Please, find attached my pass. >

On Feb 19, 2009, at 8:26 PM, 任坤 wrote: > hi, Dear Evan Cheng: > > My cpu is i32 embeded CPU. I define pseudo register pair registers. > > In mytargetRegisterInfo.td: > def T0: RegisterWithSubRegs<"t0",[R0,R1]>; > ... > def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] > > In mytargetISelLowering.cpp: > I define i1, i8 ,

Hi Sergei, It seems to me that you can represent the semantics of a conditional instruction by adding a use of the conditionally defined register to the instruction. The value of the output register of an instruction is either the value of the instruction if it was conditionally executed or the value of the output register before the instruction. The Bundle would be: BUNDLE %PC<imp-def>,

On Thu, Jul 6, 2017 at 7:00 AM, Davide Italiano <davide at freebsd.org> wrote: > On Wed, Jul 5, 2017 at 3:59 PM, Johan Engelen via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I just found an optimization regression regarding simple > > dataflow/constprop analysis: > > https://godbolt.org/g/Uz8P7t > > > > This code >