similar to: [LLVMdev] Target code size

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: a6bd6c9333397f5a0e2667d4d82fef8c970108f2 Add linux-next specific files for 20240328 Error/Warning: (recently discovered and may have been fixed) ERROR: modpost: "memcpy" [crypto/chacha20poly1305.ko] undefined! ERROR: modpost: "memcpy" [fs/efs/efs.ko] undefined! ERROR:

Hi, I'm trying to add a target-specific builtin to clang and llvm. I was able to do that for many different "regular" instructions, however I encountered some issues with one specific. The instruction is syscall, which should force the compiler to act the same way as with regular calls (save registers, return address etc), except that this instruction takes just the syscall number as

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 4118d9533ff3a5d16efb476a0d00afceecd92cf5 Add linux-next specific files for 20240411 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202404120101.dAQBAzh3-lkp at intel.com Error/Warning: (recently discovered and may have been fixed) huge_memory.c:(.text+0x1778): undefined reference

On 03/09/2017 12:57 PM, Krzysztof Parzyszek wrote: > On 3/9/2017 12:47 PM, Hal Finkel wrote: >> >> On 03/09/2017 12:28 PM, Krzysztof Parzyszek via llvm-dev wrote: >>> We could add intrinsics to extract/insert a bitfield, which would >>> simplify a lot of that bitwise logic. >> >> But then you need to teach a bunch of places about how to simply them,

Hi Language Lawyers! In PR23827 ( https://llvm.org/bugs/show_bug.cgi?id=23827 ), a bitwise op on booleans is considered equivalent to a logical op: if ((x < 3) & (y > 10)) effectively becomes: if ((x < 3) && (y > 10)) where x and y are of type 'int'. The second statement (&&) requires short-circuit evaluation to bypass the y comparison when the x

F_SETFD takes an "int", so it stands to reason that FD_CLOEXEC expands to an "int". In turn, it's bad hygiene to manipulate the sign bit of (signed) integers with bit operations: ~FD_CLOEXEC Convert FD_CLOEXEC to "unsigned int" for the bitwise complement operator: ~(unsigned)FD_CLOEXEC The bitwise complement then results in an "unsigned int".

Kenneth Uildriks wrote: > On Wed, Nov 11, 2009 at 2:10 PM, Nick Lewycky <nicholas at mxc.ca> wrote: >> Kenneth Uildriks wrote: >>> On Tue, Nov 10, 2009 at 6:10 PM, Talin <viridia at gmail.com> wrote: >>>> In my case, I've been attempting to build a target-neutral frontend. In >>>> my >>>> tool chain, the target is specified at

Hello, I am new to LLVM and I am not sure whether I am writing to the right distribution list or not. Please let me know if this is not the right distribution list. Question: - I am having hard time lowering ADD instructions for different purposes. Basically, I want to have different machine instruction for pointer addition vs scalar addition. I am having hard time mapping LLVM add to my machine

Hello, I am new to LLVM and I am not sure whether I am writing to the right distribution list or not. Please let me know if this is not the right distribution list. Question: - I am having hard time lowering ADD instructions for different purposes. Basically, I want to have different machine instruction for pointer addition vs scalar addition. I am having hard time mapping LLVM add to my machine

I'm writing a back-end for a target in which all dyadic instructions support one register and one memory operand but only some instructions support two register operations. For example ADDrm and ADDrr are supported, ANDrm is supported but ANDrr isn't. I've written descriptions for ADDrm, ADDrr and ANDrm in my InstrInfo.td file but instruction selection fails when presented with an AND

Hi, Thanks everybody that showed up in our talk at the LLVM dev meeting and to those that provided feedback so far. The slides are already online: http://llvm.org/devmtg/2016-11/Slides/Lopes-LongLivePoison.pdf The main question that some people raised was whether we could have bitwise poison instead of value-wise poison, since that semantics seems to be more natural as values continue to be just

Hi, I just noticed that Compiz' window base size calculation in the function recalcNormalHints() is broken. If both PMinSize and PBaseSize are set, the base size is overwritten by the minimum size first and after that the minimum size is overwritten by the base size again. This leads to the base size information being completely lost. I have attached a patch which fixes this problem, however,

I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts sounds similar to yours for 32-bit shifts. I

Hi Andy, Andrew Trick wrote: > Sanjoy, > > This looks very close to my understanding of the statepoint design trajectory when you first introduced it. It’s great that you followed through and took the time to formalize the IR semantics. It’s been a couple years since I’ve thought about it so I may ask some obtuse questions. > > I think he subject line is wrong though! Did

On 04/01/2013 12:31 PM, Chandler Carruth wrote: > On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com > <mailto:nrotem at apple.com>> wrote: > > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if > the attributes changed). Do you have another solution in mind ?

What I meant was to write your own expansion pass and run it after the scheduler passes, e.g. in the pre-emit stage. > if (addPreEmitPass()) printAndVerify("After PreEmit passes") Though if it's too hacky for you then fair enough. Amara On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote: > Amara, > > first, thank you for answering. but I found

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 727900b675b749c40ba1f6669c7ae5eb7eb8e837 Add linux-next specific files for 20240403 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202404031246.aq5Yr5KO-lkp at intel.com https://lore.kernel.org/oe-kbuild-all/202404031346.wpIhNpyF-lkp at intel.com

The new SUBREG target-independent instructions aren't getting mayLoad/mayStore flags set correctly. For example, in the generated X86GenInstrInfo.inc file, there is only one entry for INSERT_SUBREG: { 5, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, OperandInfo107 }, // Inst #5 = INSERT_SUBREG THe sixth field is zero, which means it doesn't have the the

Hi! The Netfilter project proudly presents: libnftnl 1.1.6 libnftnl is a userspace library providing a low-level netlink programming interface (API) to the in-kernel nf_tables subsystem. This library is currently used by nftables. See ChangeLog that comes attached to this email for more details. You can download it from: http://www.netfilter.org/projects/libnftnl/downloads.html

On Mar 18, 2008, at 6:12 PM, Dan Gohman wrote: > The new SUBREG target-independent instructions aren't getting > mayLoad/mayStore flags set correctly. > > For example, in the generated X86GenInstrInfo.inc file, > there is only one entry for INSERT_SUBREG: > > { 5, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, > OperandInfo107 }, // Inst #5 =