similar to: [LLVMdev] Target Triple Changes

Displaying 20 results from an estimated 20000 matches similar to: "[LLVMdev] Target Triple Changes"

2011 Jan 23
0
[LLVMdev] Target Triple Changes
Hi Renato, > 1. Some ARM triples "arm*-none-eabi" don't get properly recognized, > so Clang doesn't generate correct AAPCS (soft and hard) calls and > don't pass the correct triple to LLC. in order to have "eabi" be properly recognized by LLVM, it is enough to add "eabi" as a valid environment value. Then Triple::Normalize will automatically
2014 Jun 19
2
[LLVMdev] [PATCH] triples for baremetal
Eric, Attached are patches for llvm and clang that implement this. I've made 'none' a component that must be added explicitly (i.e. don't turn arm-eabi into arm--none-eabi, but rather turn it into arm--unknown-eabi) to try to reduce surprises. It also keeps the normalization logic a bit simpler than it would otherwise have to be. SPIR triples were one place where I was
2014 Jun 17
4
[LLVMdev] triples for baremetal
[+llvmdev, -llvm-dev] (Oopsies, llvmdev doesn't have a hyphen in it like all the others do) On 6/17/14, 10:45 AM, Jonathan Roelofs wrote: > [+llvm-dev, cfe-dev] > > Was "Re: [PATCH] ARM: allow inline atomics on Cortex M" > > On 6/17/14, 10:42 AM, Jonathan Roelofs wrote: >> >> >> On 6/17/14, 9:35 AM, Renato Golin wrote: >>> On 17 June 2014
2012 Feb 19
1
[LLVMdev] LinkModules triple/datatype mismatch warnings a bit strict?
Hi, I'm fairly new at poking around in llvm internals so if you find misconceptions / problems with the below let me know, this is just how I've understood this so far. When doing a build which uses functionality from LinkModules to combine bitcode from different versions of LLVM, or between LLVM-GCC (I know) and Clang, I've noticed that multiple warnings which sometimes seem
2016 Mar 12
4
clang triple and clang target
> > I assume with target you mean the backend? Consider the x86 backend. It > supports 32bit and 64bit mode, with the GNU x32 ABI in between. There > are three different executable formats support (ELF, PE, MachO) with > different constraints. Some platforms require 32bit alignment of the > stack, others require 128bit alignment. The list goes on. The triple > specifies >
2016 Jul 05
2
Representing MIPS ABI information in the triple as ARM/X86 do for EABI/EABIHF/X32
Hi Eric, It's the unsolved problems on the pass-MCTargetOptions-everywhere path that are my main concern with that approach rather than the amount of work. The first problem is that the result of IRObjectFile::CollectAsmUndefinedRefs() depends on the ABI but IRObjectFile doesn't know it. How would you deliver the ABI to IRObjectFile? The second problem is that IRLinker will link
2013 Dec 11
1
[LLVMdev] [PATCH] Select correct embedded libclang_rt on Darwin
> When you decide to work on MachO/Darwin, I want to discuss the problems with ELF vs. EABI (http://llvm.org/PR18187). Well, I'm doing it now to some extent (working on disentangling the ARM backend's various uses of isTargetIOS, isTargetDarwin, isMoonFull as a starting-point). The thing is, the main advantage of Triples is that they're largely GCC-compatible. Without that
2016 Jun 24
7
Representing MIPS ABI information in the triple as ARM/X86 do for EABI/EABIHF/X32
Hi, Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in the triple and that's the only information MipsMCAsmInfo has. This would be fine if it N32 was
2015 Sep 15
3
The Trouble with Triples
On 15 September 2015 at 19:34, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > We can go further with this analogy too. For example, let's say John Smith > with the SSN Y also answers to the name Rameses. This is the problem that > Renato is working on. Renato needs to be able to see the name Rameses and > map this to the correct John Smith (or at least someone very
2013 Dec 09
0
[LLVMdev] [cfe-dev] ARM EABI and modulo
Hi Joerg, > At the moment, this will call __modsi3 and __umodsi3, even though those > functions are not part of AAPCS. Should this be considered a lowering > bug in the ARM target? LLVM actually supports both variants, depending on the target. The __aeabi_* functions are part of the ARM "runtime ABI" and largely independent of AAPCS. For whatever reason, Linux (& Darwin)
2015 Jul 30
2
[LLVMdev] The Trouble with Triples
On 30 July 2015 at 15:30, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > I haven't fully researched why the triple is there but one reason is to make backends target the same target as the frontends. Consider the case where clang is used to generate IR and then llc is used to compile it. We currently use the information in the IR to set the GNU triple, the target features,
2012 Jan 09
0
[LLVMdev] generating ELF files on non-ELF platforms with MC
Hi, > Would it be OK to add "ELF" to Triple::EnvironmentType? It seems like a plausible choice since MachO is there. On the other hand, I'm not sure whether it makes sense to make it mutually exclusive with the other members of EnvironmentType (GNU, GNUEABI, EABI). EABI and GNUEABI imply ELF. GNU in practice does not need to imply ELF, but is used in the ARM world as "the
2014 Jun 23
4
[LLVMdev] [cfe-dev] [PATCH] triples for baremetal
Hi Jonathan, The main issue with your patch is that it can change user expected behaviour, and I can't tell you what is the expected behaviour in Darwin or BSD. If people usually use "unknown" in triples, this will break their builds. If not, this could break the build of someone who does. My advice is to create a "default" mechanism for the affected targets, something
2009 Oct 05
2
[LLVMdev] getting gold plugin to work?
On Mon, Oct 5, 2009 at 2:21 PM, Rafael Espindola <espindola at google.com> wrote: > 2009/10/4 Sandeep Patel <deeppatel1987 at gmail.com>: >> There needs to be a build step >> somewhere in llvm-gcc that copies it into libexec/<gcc >> poop>/libLLVMgold.so, but I've been doing that manually for now. > > Yes, this is bad. The problem is that we build
2013 Oct 15
2
[LLVMdev] Unwanted push/pop on Cortex-M.
Hi Andrea, That is because the LR is the fixed register as per the http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042e/IHI0042E_aapcs.pdf and out_char() function is not the leaf function ,Hence compiler tends to save and restore the LR and the save and restore of register r11 is to align stack for 8 bytes as per ARM EABI. Thanks ~Umesh On Tuesday, October 15, 2013, Umesh Kalappa
2016 Apr 18
2
[cfe-dev] [libunwind] __ELF__ macro for arm-none-eabi
On 18 April 2016 at 16:33, Silviu Baranga <Silviu.Baranga at arm.com> wrote: > Doing a grep "eabi" * -R | grep darwin in llvm I found the test divmod-eabi.ll > which uses the triple armv7-apple-darwin-eabi. What format does that have? Certainly not ELF. :) But I didn't mean "has eabi on triple", but "is in none-eabi mode", which may have to check a
2010 Sep 17
2
[LLVMdev] Support for ARM Run-Time ABI
Dear all, I just sent a patch to llvm-commits about ARM RT-EABI support when choosing "arm/thumb*-eabi-*" triple. It involves three changes described in the path: 1. Floating point helpers (instead of GNU ones). This is supported by GCC as well, in EABI mode. 2. Reminder lowering, using ABI helper too. 3. Memset, changing the order of arguments, as required by the ABI. Please
2016 Jun 29
0
Representing MIPS ABI information in the triple as ARM/X86 do for EABI/EABIHF/X32
On 24 June 2016 at 06:02, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > Hi, > > Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in
2013 Nov 26
3
[LLVMdev] Targeting ARM Cortex-a9 from x86_64 with clang
Hi, here's the canonical helloworld.c #include<stdio.h> int main() { printf("Hello World"); return 0; } In accordance with the cross-compilation LLVM documentation [1], I am trying to target the ARM on the Zedboard [2]. It is an ARM Cortex-A9. The machine I am compiling on is an x86_64 Fedora Linux machine, using clang 3.3. I am failing to generate an executable,
2016 Jun 30
1
Representing MIPS ABI information in the triple as ARM/X86 do for EABI/EABIHF/X32
Thanks Renato and Rafael. > On 24 June 2016 at 06:02, Daniel Sanders <Daniel.Sanders at imgtec.com> > wrote: > > Hi, > > > > Having recently enabled IAS by default for the MIPS O32 ABI, I'm now > trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not > currently possible to enable IAS by default for the N64 ABI without also > enabling