similar to: [LLVMdev] [LLVMDev] Block Layout

I have a live interval, and I would like to find out what SlotIndex the next use the register will occur? Is there any way to map a live interval back into instructions or SlotIndexes or blocks used by? - Thanks Jeff Kunkel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110120/fd429dbd/attachment.html>

I am looking for the slot index of a register around the given slot index Min. Is there a better way than the linear search: ... findDefUsesAroundIndex( LiveInterval* li, SlotIndex Min ) ... for( MachineOperand * mo = MRI->getRegUseDefListHead(li->reg); mo; mo = mo->getNextOperandForReg() ) { SlotIndex si = SI->getInstructionIndex( use.getOperand().getParent() ); if(

Spiller::Spill( LiveInterval *li, SmallVectorImpl<LiveInterval*> &newIntervals, const SmallVectorImpl<LiveInterval*> &spillIs ); has two reference vectors which contain a small list of Live Intervals. What is the register allocator's job to do with these intervals other than analysis. What more needed other than to know

I understand the mechanics. I don't know why a lesser weight is better than a greater weight. On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Oct 28, 2010, at 4:05 PM, Jeff Kunkel wrote: > >> I was studying the basic register allocator, and I am wondering why >> "LessSpillWeightPriority" priority was used over the

On Jan 20, 2011, at 5:37 AM, Jeff Kunkel wrote: > I have a live interval, and I would like to find out what SlotIndex the next use the register will occur? Is there any way to map a live interval back into instructions or SlotIndexes or blocks used by? Not really, you have to use the use-def chain. See SplitAnalysis::analyzeUses(). /jakob -------------- next part -------------- A non-text

I have noticed quite a few changes regarding register allocation. I am wondering will there be support for radically different data structures other than the LiveIntervals, Virtual Register Map, etc? I have build a custom data structure which has it's own intermediate representation like live-intervals, but much more conducive for my allocation algorithm. I do not know if LiveIntervals can

Let me rephrase my question. The live intervals have a weight associated with them. What does this weight exactly represent? Thanks Jeff Kunkel On Thu, Oct 28, 2010 at 7:41 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > I understand the mechanics. I don't know why a lesser weight is better > than a greater weight. > > > On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund

Hi Jeff, There is an algorithm to build the dominator tree that is O(n2), where n is the number of nodes on the control flow graph. I believe exists another that is linear, but I don't which one of them is implemented in LLVM. The problem is that the branch predictor requires post dominance information. None of the LLVM basic passes require post dominance information (AFAIK), hence it is

You said it was expensive, but if you had to put a big-o estimate on it, what would it be? -Thanks Jeff Kunkel On Tue, Nov 2, 2010 at 8:54 PM, Andrei Alvares <logytech at gmail.com> wrote: > Hello Jeff, > > On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > > My god! I would love a branch predictor! It would simplify many aspects > of >

On Oct 28, 2010, at 9:40 AM, Jeff Kunkel wrote: > I have noticed quite a few changes regarding register allocation. I am > wondering will there be support for radically different data > structures other than the LiveIntervals, Virtual Register Map, etc? Not any more than we already have. If anything, these data structures are going to be simplified. For instance, VirtRegMap's

Jeff Kunkel <jdkunk3 at gmail.com> writes: > Spiller::Spill( LiveInterval *li, >                           SmallVectorImpl<LiveInterval*> &newIntervals, >                           const SmallVectorImpl<LiveInterval*> &spillIs ); > > has two reference vectors which contain a small list of Live > Intervals. What is the register allocator's job to do

Bump: Does profiling / run time information exist when dealing with machine basic blocks? Thanks, Jeff Kunkel On Tue, Sep 28, 2010 at 9:51 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > How do I find the profiling or run time information for machine basic > blocks from a machine function? There are quite a few optimization > that may be preformed with this information, when it

I'm just running VS 10 in debug mode. In a step by step set up: 1. I download the svn 2. I make my changes 3. I compile the libraries 4. I make changes to the code within my project 5. I compile my code, and I re-link llc with my changed files. 6. I repeat 4,5, and 6 until it finally works. - Jeff Kunkel On Tue, Nov 2, 2010 at 1:21 PM, Óscar Fuentes <ofv at wanadoo.es> wrote: >

Hello Jeff, On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > My god! I would love a branch predictor! It would simplify many aspects of > my register allocator. The branch predictor of the implementation is not as accurate as the one from the paper, but it is close enough. Unfortunately, the branch predictor is a very expensive pass, because it relies on

It is at the end allowing for oddities like debug info and multiple branches. You might want to look at AnalyzeBranch. On Sep 2, 2010, at 4:19 PMPDT, Jeff Kunkel wrote: > Is there any way to tell where in the Instruction list, the branch > to the other MachineBasicBlock happens? I know in the BasicBlock had > a nice api for it. > > Thanks, > Jeff Kunkel > > On Thu,

Jacob, have you completed the topological sorting or the registers? It seems I iterate through sub/alias-registers quite often, and I think a performance gain might occur if the sub-registers were grouped better. Thanks, Jeff Kunkel

How do I find the profiling or run time information for machine basic blocks from a machine function? There are quite a few optimization that may be preformed with this information, when it exists. Thanks, Jeff Kunkel

I ran cmake to build the visual studio projects. Then I included my code under the Visual Studio interface, but I placed my code separate from the CodeGen code. Visual studio was smart enough to compile and link in my code into the CodeGen library. Thus, I did not need to add my code into the same directory as the CodeGen files, and I did not need to change the CMakeList.txt. The offical name is

I am plugging this into my code. If someone wants to take it out and add it to the llvm library, it's a simple Linear Congruential Generator, but here it is: typedef struct random_number_gen { unsigned a, c, seed, m; random_number_gen( unsigned seed, unsigned modulo ) : seed(seed), m(modulo) { unsigned primes[] = { 2, 3, 5, 7, 11, 13, 17, 19, 23, 29 };

Hello, does LLVM already have a Random Number Generator built into it's library somewhere? I know code generation is suppose to be deterministic, but when producing a random number can be deterministic if the random number generator is also deterministic. - Thanks - Jeff Kunkel