similar to: [LLVMdev] [LLVMDev] Live Intervals and Finding the next usage

I am looking for the slot index of a register around the given slot index Min. Is there a better way than the linear search: ... findDefUsesAroundIndex( LiveInterval* li, SlotIndex Min ) ... for( MachineOperand * mo = MRI->getRegUseDefListHead(li->reg); mo; mo = mo->getNextOperandForReg() ) { SlotIndex si = SI->getInstructionIndex( use.getOperand().getParent() ); if(

On Jan 20, 2011, at 5:37 AM, Jeff Kunkel wrote: > I have a live interval, and I would like to find out what SlotIndex the next use the register will occur? Is there any way to map a live interval back into instructions or SlotIndexes or blocks used by? Not really, you have to use the use-def chain. See SplitAnalysis::analyzeUses(). /jakob -------------- next part -------------- A non-text

Hi Lang, Just one more quick question. in LiveIntervalAnalysis.cpp In SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) Did you really mean to use for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg), UE = MRI.use_nodbg_end(); UI != UE; UI.skipInstruction()) {} Aren't we currently dealing with units,

Is there an easy way to obtain all liveout variables of a basic block? Liveins can be found for each MachineBasicBlock, but I can only find liveouts for the whole function, at MachineRegisterInfo. Do I need to find them out manually?

Lang, I think I am getting closer to understanding this. The findLastUseBefore() should probably look something like this: // Return the last use of reg between NewIdx and OldIdx. SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) { SlotIndex LastUse = NewIdx; if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitRootIterator Roots(Reg,

Hi all, I'm tracking down a register allocation problem and I'm trying to understand this piece of code in InlineSpiller::spillAroundUses: // Find the slot index where this instruction reads and writes OldLI. // This is usually the def slot, except for tied early clobbers. SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot(); if (VNInfo *VNI =

Because I feel bad for giving a non-answer: An easy way to find if a virtual register is alive after the basic block is to While iterating over the virtual registers - Check to see if the virtual register's "next" value exists outside of the basic block. for instance: std::vector<unsigned> findLiveOut( MachineBasicBlock * mbb ) { std::vector<unsigned> liveout; for(

2015-05-27 10:59 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: > > On 2015 May 27, at 10:24, Chandler Carruth <chandlerc at google.com> wrote: > > > >> On Wed, May 27, 2015 at 8:15 AM Chris Lattner <clattner at apple.com> > wrote: > >>> On May 26, 2015, at 11:20 PM, Quentin Colombet <qcolombet at apple.com> > wrote:

> On 2015 May 27, at 14:01, Alex L <arphaman at gmail.com> wrote: > > > > 2015-05-27 10:59 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: > > On 2015 May 27, at 10:24, Chandler Carruth <chandlerc at google.com> wrote: > > > >> On Wed, May 27, 2015 at 8:15 AM Chris Lattner <clattner at apple.com> wrote: > >>>

HI Is there a public function equivalent of calling getIndex I would like to use some sort of starting slot info of a live interval in some pass. I need a way of comparing which virtual register is associated with an earlier source line without relying on any debug info. The relative order is preserved in my case. thanks shrey

> On May 27, 2015, at 2:18 PM, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > > >> On 2015 May 27, at 14:01, Alex L <arphaman at gmail.com> wrote: >> >> >> >> 2015-05-27 10:59 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: >>> On 2015 May 27, at 10:24, Chandler Carruth <chandlerc at google.com>

Do you know any backend that implement instructions as a flag modifier in instruction ? Thank, Vincent Lejeune ----- Mail original ----- > De : Jakob Stoklund Olesen <stoklund at 2pi.dk> > À : Vincent Lejeune <vljn at ovi.com> > Cc : "llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu)" <llvmdev at cs.uiuc.edu> > Envoyé le : Lundi 6 août 2012 20h06 >

Hi, R600 hardware (Radeon gfx card) does neither have a NEG nor an ABS instruction ; however any sources operand can be negated/abs'd by setting a bit for every source operand in the final bytecode (but not DST). A good way of modeling this behavior in LLVM is by using TargetFlag on operand. Currently the R600 LLVM backend in Mesa lower NEG and ABS DAG instruction to a MOV + TargetFlag using

Hi Sergei, Andy, Sorry - I got distracted with some other work. I'm looking into this and PR13719 now. I'll let you know what I find out. Sergei - thanks very much for the investigation. That should help me pin this down. Cheers, Lang. On Tue, Aug 28, 2012 at 2:33 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Andy, Lang, > > Thanks for the suggestion. >

Andy, Lang, Thanks for the suggestion. I have spent more time with it today, and I do see some strange things in liveness update. I am not at the actual cause yet, but here is what I got so far: I have the following live ranges when I start scheduling a region: R2 = [0B,48r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)...

On Aug 6, 2012, at 11:00 AM, Vincent Lejeune <vljn at ovi.com> wrote: > Ok. > > I tried to do it using a pass after register allocation, lowering NEG/ABS instructions. > However I met a problem : apparently getNextOperandForReg() can returns a MachineOperand before the one I'm processing. > > The following code snippet : > > > void

Hello LLVM Developers, We are working on extending currently available register rematerialization to include cases where sequence of multiple instructions is required to rematerialize a value. We had a discussion on this in community mailing list and link is here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/subject.html#104777 >From the above discussion and studying the code we

Thanks for your last reply. Could I understand the way to adding a pass (built into the llvm rather than dynamic loadable) includes: 1. Declaring a creator function for this pass 2. Implementing the creator function for this pass 3. Instantiating this pass and get a object of it 3. Register this pass into the PassRegistry Then, for a built-into bytecode pass, task 1(declaration of the

On Wed, May 27, 2015 at 8:15 AM Chris Lattner <clattner at apple.com> wrote: > On May 26, 2015, at 11:20 PM, Quentin Colombet <qcolombet at apple.com> > wrote: > > +1. > > Could those two be subdirectories of one “Machine-Related-Stuff” directory? > E.g., > MachineStuff/IR > MachineStuff/CodeGen > > Where MachineStuff is something meaningful :). >

On Aug 6, 2012, at 11:16 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > The getNextOperandForReg() function isn't used anywhere, Should we remove it? -Jim