similar to: [LLVMdev] Modifying the patterns/ instruction selection phase in LLVM 2.7

On 1/20/11 12:27 PM, Venkatraman Govindaraju wrote: Just out of curiosity, have either of you considered writing an LLVM transform that simply replaces these call instructions with inline assembly code that does what you want? If that works, it seems much simpler than modifying/enhancing the code generator. -- John T. > I have similar requirements for my project. This is what I do. >

For my case, I can't replace these call instructions with inline assembly code because I need to encode the registers into the "number". For instance, if the call instruction is %result = call i32 @foo(i32 %a) and the result is assigned to register %l0 and the variable "a" to register %l1, then I encode all foo, %l0 and %l1 and generate a sethi instruction. thanks,

I have similar requirements for my project. This is what I do. 1. Add a new intrinsic function to LLVM that corresponds to "functions with particular type of function names". The steps to create intrinsic function is documented in http://llvm.org/docs/ExtendingLLVM.html#intrinsic. 2. Create a lowering pass that lowers "functions with particular type" ( eg. p0, p1) to

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

Hi, There are some generated Sparc assembly code like this: main: ! @main ! BB#0: save %sp, -112, %sp sethi 0, %l0 or %g0, 5, %l1 st %l0, [%fp+-4] st %l1, [%fp+-8] st %l1, [%fp+-12] sethi %hi(.L.str), %l1 ld [%fp+-8], %o1 add %l1, %lo(.L.str), %l1 or %g0, %l1, %o0 call printf nop ld [%fp+-12], %o2 ld [%fp+-8], %l2 sethi %hi(.L.strQ521), %l3 add

Hello. I have been trying to check, how llvm works on Solaris recently. First I have tested lli, whitch seems to execute the bytecode generated on Linux without any problems. However, llc has failed to generate valid SPARC assembler code even on the helloworld example. Here is the generated code: sakharov at trillian:~$ cat ./test.s .text .align 16 .globl main

________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Friday, September 19, 2008 10:49 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Custom Opcodes versus built-in opcodes On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: I am using lowering instructions and using custom opcodes that

On Sep 19, 2008, at 11:35 AM, Villmow, Micah wrote: > Make sure to use DAG.getTargetNode() with custom opcodes. "target" > nodes are encoded with an implicit delta added to their enum value. > > Is this documented anywhere that getTargetNode is the preferred > method to use in a Custom Lowering function? Even the other backends > use getNode in their lowering

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC

Hi I am new to llvm and Linux (I am using ubuntu 10) My aim is to add backend to llvm. I install llvm using $ sudo apt-get install llvm and I am able to understand what I read about Writing an LLVM Compiler Backend. I have seen the assembly codes of the targets on llvm using llc. What I need now is to change some of the TableGen files of one of the target like SparcInstrInfo.td.  So I

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }

On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: > I am using lowering instructions and using custom opcodes that I can > more easily directly map to my backend. These opcodes are then used > to emit a custom set of instructions into the MachineBasicBlock. > I’ve been able to get one to work correctly, however, I’ve ran into > an issue where my second one is being

Have you added the $LLVM_INSTALL_DIR/bin to your PATH environment variable? Regarding changing a particular backend, check the documentation in http://llvm.org/docs/WritingAnLLVMBackend.html http://llvm.org/docs/CodeGenerator.html A few LLVMdev meetings have good talks to give you a good enough idea. http://llvm.org/devmtg/ Cheers, Raghu. ----- Original Message ----- From: "Teklu

Hi list, I added custom code to eliminate frame index references. I replace each FI reference with a subtraction from my frame pointer register (just like ebp in x86). Its result is stored in another register which is used by the load/store instructions. Nevertheless, this operation gives me redundant subs that I would like to remove after all fi references have been eliminated. For example:

On Jan 7, 2011, at 2:36 PM, Venkatraman Govindaraju wrote: > When I run LLC with option "-O0 -march=sparc" on following testcase, > fast register allocator crashes with "UNREACHABLE executed" error. LLC > generates code successfully with other standard register allocators > available. I haven't investigated the Sparc backend specifically but... My guess is

I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead of my opcode. DValue

Hi all, I am working with the "LowerCall" function, and trying to figure out the types of all the "Outs" arguments. Specifically, I want to find out if a particular "Out[i]" argument is a pointer (of any type), or a regular data type. So far, all pointers show up as the "MVT::i32" datatype, which is not helping my cause. Is there a way to distinguish

Hi, I have the following test code print.c: #include <stdio.h> int main(){ fprintf(stderr, "Error!\n"); return 0; } I did the following on linux to cross-compile it for Sparc architecture: clang -m32 -c print.c -emit-llvm -o print.bc (or llvm-gcc -m32 -c print.c -emit-llvm -o print.bc) llvm-dis < print.bc -o print2.bc llc -march=sparc -mcpu=v8 print2.bc -o print_s.s if

Hi Raghu, > I am working with the "LowerCall" function, and trying to figure out the types of all the "Outs" arguments. Specifically, I want to find out if a particular "Out[i]" argument is a pointer (of any type), or a regular data type. So far, all pointers show up as the "MVT::i32" datatype, which is not helping my cause. Is there a way to distinguish

Hi, Chris > That is target independent code, so you should not put sparc specific changes there.  It sounds like one of the sparc-specific target hooks is wrong. Since sparc does not provide any hooks for operation of branches (e.g. AnalyzeBranch and friends) it might be possible that generic codegen code is broken in absence of these hooks. -- With best regards, Anton Korobeynikov Faculty