similar to: [LLVMdev] PostRAScheduling for x86

On Jan 11, 2011, at 2:56 PM, JG wrote: > I am trying to understand why PostRAScheduling is done only for ARM. Is there any limitation which prevents this from being done for x86 ? It's a 10% increase in overall compile time, and it does not help very much for x86. The out-of-order execution on new x86 chips hide any benefits from late scheduling. /jakob

On 1/14/2013 3:16 PM, Jakob Stoklund Olesen wrote: > > On Jan 14, 2013, at 12:56 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: >> >> My question is: is this something that was a part of the design? > > Yes, the register allocator only deals in full-width virtual registers, so any copies or spills created will operate on the full register. I see.

Hi, Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the spiller's class? Thanks, -- Silvio Ricardo Cordeiro --------------

On Aug 15, 2010, at 5:12 PM, Silvio Ricardo Cordeiro wrote: > Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the

I will be removing RegAllocLinearScan and VirtRegRewriter from trunk shortly after we cut the 3.0 release branch. LLVM 3.0 will still ship with the linear scan register allocator, but the default will be the new greedy allocator. Linear scan can be enabled by passing '-regalloc=linearscan -join-physregs' to llc. RegAllocLinearScan and VirtRegRewriter need to go away soon because they

Hey all, I've found a bug in either the PBQP register allocator or in VirtRegRewriter. I'm observing this assertion in VirtRegRewriter::rewrite() fail: unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM->getPhys(VirtReg); ... assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); Indeed there is a case where

Is there any specific documentation on this? Is there a point of contact for this file that I might bug? So I have an instruction that needs noops inserted and it appears that the noops are being inserted in the EmitSchedule function of the PostRAScheduler. From the loop in EmitSchedule it looks like it's inserting noops whenever SUnit is NULL. I don't see anything in the DAG that appears

On Jan 14, 2013, at 1:39 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > On 1/14/2013 3:16 PM, Jakob Stoklund Olesen wrote: >> >> On Jan 14, 2013, at 12:56 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: >>> >>> My question is: is this something that was a part of the design? >> >> Yes, the register allocator

On Oct 7, 2011, at 8:14 AM, Jonas Paulsson wrote: > Hi, > > I think I've found a bug in this method. > > I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. > > For the def-operand, with a subregindex, an implicit-use operand was added with this code: > >

Dear R community, I am trying to fit an nlme model where I want to estimate the fixed effects of two treatments on the parameters on the following equation Photo~(a*(1-exp(-c*PARi/a)))-b I was able to fit a simple model without covariates following the method described in Mixed-Effects Methods and Classes for S and S-PLUS, version 3.0, but when I add the covariates, I get the error "

On May 3, 2011, at 3:24 PM, David A. Greene wrote: > Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > >> On May 3, 2011, at 12:03 PM, David A. Greene wrote: > >>> Certainly. I would ask that we keep linearscan around, if possible, as >>> long as there are significant regressions like this. Our customers tend >>> to really, really care about

Hi, I think I've found a bug in this method. I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. For the def-operand, with a subregindex, an implicit-use operand was added with this code: VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); MI.addOperand(MachineOperand::CreateReg(VirtReg,

Thanks Lang! Here's another question: I'm trying to process this input: int main() { return 0; } but I'm getting an error Assertion `!Fn.getRegInfo().getNumVirtRegs() && "Regalloc must assign all vregs"' failed. At the start of runOnMachineFunction I call Fn.getRegInfo().getNumVirtRegs(); and find that there is 1 virtual register. However,

Hi, I am trying to take 16 bit memory reads and combine them to a single 32 bit read. I am having trouble to make the code simply read 32 bytes and the use the subregisters accordingly, without unnecessary copying. I have tried two techniques, in the MachineFunction: 1. replace the MachineOperands in the users of the data with the new register/subregister index. This yields an assert failure

On Thursday 04 June 2009 13:57, Lang Hames wrote: > R.I.P. SimpleRewriter. If anyone needs it resurrected let me know. > > This leaves LocalRewriter (the default) and the new TrivialRewriter, > which is for use only with the new in-place spilling framework. This > framework appears (if you squint just right) to be basically > functional now, but it produces awful code. If you

Hi Susan, I'm having trouble reproducing that error on my end, but I think the problem is probably that you're not using the VirtRegRewriter infrastructure. What your allocator needs to do is populate the virtual register mapping (VirtRegMap pass) with your allocation, rather than rewriting the registers directly through MachineRegisterInfo. Have your allocator require and preserve the

I've been testing alpha4, and every once in a while my client (Thunderbird 1.5 RC1) tells me the dovecot isn't a valid IMAP4 server. This is usually (maybe always) when I first bring up the client up. If I just ask the client to get the mail again, it does so happily (without any errors). I must say I found dovecot as a pleasant surprise. We have been using UW. Which didn't

Hello, what could be causing the issue of poor sound quality ? Some calls, certainly not all of them, sound like if the caller is standing next to a very busy road with lots of cars passing. To be clear : the person calling is not standing next to a highway. But there seems to be a noise "on the line" of busy highroad that makes that the caller can not be understood. What can be

Hi all, These days I am working on a feature designed to insert nops for IA code generation that will provide performance improvements and performance stability. This feature will not affect other architectures. It will, however, set up an infrastructure for other architectures to do the same, if ever needed. Here are some examples for cases in which nops can improve performance: 1. DSB

Hello Everyone, We are looking for solutions where the transcoding is abstracted away from our * box (i.e., to the network layer) using some carrier grade gateway, or router. The reason for my post is to know about solutions people have used in the past, and how it fits into their overall architecture. Our transcoding needs consists mainly of u/alaw <-> g729, and gsm would also be good....