similar to: [LLVMdev] [LLVMDev] Stack Space and Removing it's Attachment to Register Allocation

Jeff Kunkel <jdkunk3 at gmail.com> writes: > Spiller::Spill( LiveInterval *li, >                           SmallVectorImpl<LiveInterval*> &newIntervals, >                           const SmallVectorImpl<LiveInterval*> &spillIs ); > > has two reference vectors which contain a small list of Live > Intervals. What is the register allocator's job to do

Thanks for the information. I still don't know how do I partition registers into different classes from the virtual registers? For instance, I have the function who which iterates over the instructions, but I don't know how to write the function which returns the different register class. void RAOptimal::Gather(MachineFunction &Fn) { // Gather just iterates over the blocks,

Let me rephrase my question. The live intervals have a weight associated with them. What does this weight exactly represent? Thanks Jeff Kunkel On Thu, Oct 28, 2010 at 7:41 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > I understand the mechanics. I don't know why a lesser weight is better > than a greater weight. > > > On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund

Spiller::Spill( LiveInterval *li, SmallVectorImpl<LiveInterval*> &newIntervals, const SmallVectorImpl<LiveInterval*> &spillIs ); has two reference vectors which contain a small list of Live Intervals. What is the register allocator's job to do with these intervals other than analysis. What more needed other than to know

I understand the mechanics. I don't know why a lesser weight is better than a greater weight. On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Oct 28, 2010, at 4:05 PM, Jeff Kunkel wrote: > >> I was studying the basic register allocator, and I am wondering why >> "LessSpillWeightPriority" priority was used over the

On Oct 28, 2010, at 9:40 AM, Jeff Kunkel wrote: > I have noticed quite a few changes regarding register allocation. I am > wondering will there be support for radically different data > structures other than the LiveIntervals, Virtual Register Map, etc? Not any more than we already have. If anything, these data structures are going to be simplified. For instance, VirtRegMap's

I have noticed quite a few changes regarding register allocation. I am wondering will there be support for radically different data structures other than the LiveIntervals, Virtual Register Map, etc? I have build a custom data structure which has it's own intermediate representation like live-intervals, but much more conducive for my allocation algorithm. I do not know if LiveIntervals can

Hello, I would like to implement a register allocation scheme which is much like the Linear Scan. It's known as Belady's Optimal Algorithm. In fact, the algorithm is very close to the linear scan algorithm, except instead of ranges, it uses points in time. I am wondering if anyone with experience implementing register optimization algorithms within LLVM would be interested in helping me.

Hi Jeff, There is an algorithm to build the dominator tree that is O(n2), where n is the number of nodes on the control flow graph. I believe exists another that is linear, but I don't which one of them is implemented in LLVM. The problem is that the branch predictor requires post dominance information. None of the LLVM basic passes require post dominance information (AFAIK), hence it is

Thank you! The pieces are starting to fall into place finally. I need to track which MachineBasicBlocks branch into other MachineBasicBlocks. How do I do it? I see a MachineOperand can hold a MachineBasicBlock*. Does this mean the instruction may branch to the MachineBasicBlock, or can it be something like an object reference? - Thanks, Jeff Kunkel On Thu, Sep 2, 2010 at 1:56 PM, Jeff Kunkel

Bump: Does profiling / run time information exist when dealing with machine basic blocks? Thanks, Jeff Kunkel On Tue, Sep 28, 2010 at 9:51 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > How do I find the profiling or run time information for machine basic > blocks from a machine function? There are quite a few optimization > that may be preformed with this information, when it

I am looking for the slot index of a register around the given slot index Min. Is there a better way than the linear search: ... findDefUsesAroundIndex( LiveInterval* li, SlotIndex Min ) ... for( MachineOperand * mo = MRI->getRegUseDefListHead(li->reg); mo; mo = mo->getNextOperandForReg() ) { SlotIndex si = SI->getInstructionIndex( use.getOperand().getParent() ); if(

Would I be correct in assuming that the alias set is defined as the registers which may reside in the same space as the register? In other words the register is either a super or sub register which holds the same physical location in the register set? Could someone please explain what the Alias set is if it is not what I described above? TargetRegisterInfo::getAliasSet( unsigned reg ) Thanks

On Nov 8, 2010, at 12:04 PM, Jeff Kunkel wrote: > Hi, while writing my register allocator, I have come across a case which confuses me because the llvm definition cannot be mapped to machine code. > > For instance I come across (1) and I reduce it to (2). However a copy instruction cannot move from EDX to CX. What mechanics in LLVM will tell me that I cannot make this move during

On Sat, Aug 28, 2010 at 16:20:42 -0400, Jeff Kunkel wrote: > What I need to know is how to access the machine register classes. Also, I > need to know which virtual register is to be mapped into each specific > register class. I assume there is type information on the registers. I need > to know how to access it. MachineRegisterInfo::getRegClass will give you the TargetRegisterClass

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

Has anyone read anything about register allocation being indeterminate? I have seen much literature about "optimal register allocation," but does anyone know a case where it is not? Thanks, Jeff Kunkel

I forgot to cc the list. On Sat, Oct 9, 2010 at 10:47 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > On Sat, Oct 9, 2010 at 10:37 AM, Michael Spencer <bigcheesegs at gmail.com> wrote: >>> On Sat, Oct 9, 2010 at 1:10 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: >>>> Hello, does LLVM already have a Random Number Generator built into >>>>

I'm just running VS 10 in debug mode. In a step by step set up: 1. I download the svn 2. I make my changes 3. I compile the libraries 4. I make changes to the code within my project 5. I compile my code, and I re-link llc with my changed files. 6. I repeat 4,5, and 6 until it finally works. - Jeff Kunkel On Tue, Nov 2, 2010 at 1:21 PM, Óscar Fuentes <ofv at wanadoo.es> wrote: >

I am plugging this into my code. If someone wants to take it out and add it to the llvm library, it's a simple Linear Congruential Generator, but here it is: typedef struct random_number_gen { unsigned a, c, seed, m; random_number_gen( unsigned seed, unsigned modulo ) : seed(seed), m(modulo) { unsigned primes[] = { 2, 3, 5, 7, 11, 13, 17, 19, 23, 29 };